ST T Computer Hardware UPSD3212A User Manual

uPSD3212A, uPSD3212C  
uPSD3212CV  
Flash Programmable System Devices with  
8032 MCU with USB and Programmable Logic  
FEATURES SUMMARY  
FAST 8-BIT 8032 MCU  
Figure 1. Packages  
40MHz at 5.0V, 24MHz at 3.3V  
Core, 12-clocks per instruction  
DUAL FLASH MEMORIES WITH MEMORY  
MANAGEMENT  
Place either memory into 8032 program  
address space or data address space  
TQFP52 (T)  
52-lead, Thin,  
Quad, Flat  
READ-while-WRITE operation for In-  
Application Programming and EEPROM  
emulation  
Single voltage program and erase  
100K minimum erase cycles, 15-year  
retention  
CLOCK, RESET, AND SUPPLY  
MANAGEMENT  
SRAM is Battery Backup capable  
Normal, Idle, and Power Down Modes  
Power-on and Low Voltage reset  
supervisor  
Programmable Watchdog Timer  
TQFP80 (U)  
80-lead, Thin,  
Quad, Flat  
www.BDTIC.com/ST  
PROGRAMMABLE LOGIC, GENERAL  
PURPOSE  
JTAG IN-SYSTEM PROGRAMMING  
16 macrocells  
Implements state machines, glue-logic,  
and so forth  
Program the entire device in as little as  
10 seconds  
A/D CONVERTER  
Four channels, 8-bit resolution, 10µs  
TIMERS AND INTERRUPTS  
COMMUNICATION INTERFACES  
2
I C Master/Slave bus controller  
Two UARTs with independent baud rate  
Six I/O ports with up to 46 I/O pins  
8032 Address/Data bus available on  
TQFP80 package  
Three 8032 standard 16-bit timers  
10 Interrupt sources with two external  
interrupt pins  
Single Supply Voltage  
5 PWM outputs, 8-bit resolution  
USB v1.1, low-speed 1.5Mbps, 3  
endpoints (uPSD3212A only)  
4.5 to 5.5V  
3.0 to 3.6V  
December 2004  
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uPSD3212A, uPSD3212C, uPSD3212CV  
TABLE OF CONTENTS  
2
I C Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
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uPSD3212A, uPSD3212C, uPSD3212CV  
Low V Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
DD  
2
I C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72  
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uPSD3212A, uPSD3212C, uPSD3212CV  
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uPSD3212A, uPSD3212C, uPSD3212CV  
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uPSD3212A, uPSD3212C, uPSD3212CV  
SUMMARY DESCRIPTION  
The uPSD321x Series combines a fast 8051-  
based microcontroller with a flexible memory  
structure, programmable logic, and a rich periph-  
eral mix including USB, to form an ideal embedded  
controller. At its core is an industry-standard 8032  
MCU operating up to 40MHz.  
Dual Flash memory banks provide a robust solu-  
tion for remote product updates in the field through  
In-Application Programming (IAP). Dual Flash  
banks also support EEPROM emulation, eliminat-  
ing the need for external EEPROM chips.  
General purpose programmable logic (PLD) is in-  
cluded to build an endless variety of glue-logic,  
saving external logic devices. The PLD is config-  
ured using the software development tool, PSD-  
soft Express, available from the web at  
www.st.com/psm, at no charge.  
A JTAG serial interface is used for In-System Pro-  
gramming (ISP) in as little as 10 seconds, perfect  
for manufacturing and lab development.  
The USB 1.1 low-speed interface has one Control  
Endpoint and two Interrupt endpoints suitable for  
HID class drivers.  
The 8032 core is coupled to Programmable Sys-  
tem Device (PSD) architecture to optimize the  
8032 memory structure, offering two independent  
banks of Flash memory that can be placed at vir-  
tually any address within 8032 program or data ad-  
dress space, and easily paged beyond 64K bytes  
using on-chip programmable decode logic.  
The uPSD321x also includes supervisor functions  
such as a programmable watchdog timer and low-  
voltage reset.  
Figure 2. Block Diagram  
uPSD321x  
(3) 16-bit  
Timer/  
Counters  
1st Flash Memory:  
64K Bytes  
8032  
MCU  
Core  
(2)  
External  
Interrupts  
Programmable  
Decode and  
Page Logic  
www.BDTIC.com/ST  
2nd Flash Memory:  
I2C  
16K Bytes  
P3.0:7  
SRAM:  
2K Bytes  
UART0  
(8) GPIO, Port A  
(80-pin only)  
PA0:7  
PB0:7  
PD1:2  
(8) GPIO, Port 3  
General  
(8) GPIO, Port B  
(2) GPIO, Port D  
(4) GPIO, Port C  
Purpose  
Programmable  
Logic,  
P1.0:7  
(8) GPIO, Port 1  
(4) 8-bit ADC  
UART1  
16 Macrocells  
PC0:7  
JTAG ISP  
MCU  
Bus  
8032 Address/Data/Control Bus  
(80-pin device only)  
(5) 8-bit PWM  
Supervisor:  
Watchdog and Low-Voltage Reset  
(8) GPIO, Port 4  
P4.0:7  
USB+,  
USB–  
Dedicated  
Pins  
VCC, VDD, GND, Reset, Crystal In  
USB v1.1  
AI10428b  
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uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 3. TQFP52 Connections  
PD1/CLKIN 1  
PC7 2  
39 P1.5/ADC1  
38 P1.4/ADC0  
37 P1.3/TXD1  
36 P1.2/RXD1  
35 P1.1/T2X  
34 P1.0/T2  
JTAG TDO 3  
JTAG TDI 4  
(1)  
USB–  
5
PC4/TERR_ 6  
USB+ 7  
33 V  
CC  
V
8
32 XTAL2  
CC  
GND 9  
31 XTAL1  
PC3/TSTAT 10  
30 P3.7/SCL1  
29 P3.6/SDA1  
28 P3.5/T1  
27 P3.4/T0  
PC2/V  
11  
STBY  
JTAG TCK 12  
JTAG TMS 13  
www.BDTIC.com/ST  
AI07423c  
Note: 1. Pull-up resistor required on pin 5 (2kfor 3V devices, 7.5kfor 5V devices).  
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uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 4. TQFP80 Connections  
PD2 1  
P3.3 /EXINT1 2  
PD1/CLKIN 3  
ALE 4  
60 P1.5/ADC1  
59 P1.4/ADC0  
58 P1.3/TXD1  
57 A11  
PC7 5  
56 P1.2/RXD1  
55 A10  
JTAG/TDO 6  
JTAG/TDI 7  
(1)  
54 P1.1/TX2  
53 A9  
USB–  
8
PC4/TERR_ 9  
52 P1.0/T2  
51 A8  
USB+ 10  
(2)  
NC  
V
11  
12  
50 V  
CC  
49 XTAL2  
48 XTAL1  
47 AD7  
CC  
GND 13  
PC3/TSTAT 14  
PC2/V  
15  
46 P3.7/SCL1  
45 AD6  
STBY  
JTAG TCK 16  
(2)  
NC  
17  
44 P3.6/SDA1  
43 AD5  
P4.7/PWM4 18  
P4.6/PWM3 19  
JTAG TMS 20  
42 P3.5/T1  
www.BDTIC.com/ST  
41 AD4  
AI07424c  
Note: 1. Pull-up resistor required on pin 8 (2kfor 3V devices, 7.5kfor 5V devices).  
2. NC = Not Connected.  
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uPSD3212A, uPSD3212C, uPSD3212CV  
Table 2. 80-Pin Package Pin Description  
Signal  
Function  
Port Pin  
Pin No. In/Out  
Name  
Basic  
Alternate  
External Bus  
AD0  
36  
I/O  
Multiplexed Address/Data bus A1/D1  
Multiplexed Address/Data bus A0/D0  
Multiplexed Address/Data bus A2/D2  
Multiplexed Address/Data bus A3/D3  
Multiplexed Address/Data bus A4/D4  
Multiplexed Address/Data bus A5/D5  
Multiplexed Address/Data bus A6/D6  
Multiplexed Address/Data bus A7/D7  
General I/O port pin  
AD1  
AD2  
AD3  
AD4  
AD5  
AD6  
AD7  
T2  
37  
38  
39  
41  
43  
45  
47  
52  
54  
56  
58  
59  
60  
61  
64  
51  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
P1.0  
P1.1  
P1.2  
P1.3  
P1.4  
P1.5  
P1.6  
P1.7  
Timer 2 Count input  
Timer 2 Trigger input  
2nd UART Receive  
2nd UART Transmit  
ADC Channel 0 input  
ADC Channel 1 input  
ADC Channel 2 input  
ADC Channel 3 input  
TX2  
General I/O port pin  
RxD1  
TxD1  
ADC0  
ADC1  
ADC2  
ADC3  
A8  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
External Bus, Address A8  
www.BDTIC.com/ST  
A9  
53  
55  
57  
75  
77  
O
O
External Bus, Address A9  
External Bus, Address A10  
External Bus, Address A11  
General I/O port pin  
A10  
A11  
O
P3.0  
P3.1  
RxD0  
TxD0  
I/O  
I/O  
UART Receive  
UART Transmit  
General I/O port pin  
Interrupt 0 input / Timer 0 gate  
control  
P3.2  
P3.3  
EXINT0  
EXINT1  
79  
2
I/O  
I/O  
General I/O port pin  
General I/O port pin  
Interrupt 1 input / Timer 1 gate  
control  
P3.4  
P3.5  
P3.6  
T0  
T1  
40  
42  
44  
I/O  
I/O  
I/O  
General I/O port pin  
General I/O port pin  
General I/O port pin  
Counter 0 input  
Counter 1 input  
2
SDA1  
I C Bus serial data I/O  
2
P3.7  
P4.0  
P4.1  
P4.2  
SCL1  
46  
33  
31  
30  
I/O  
I/O  
I/O  
I/O  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
I C Bus clock I/O  
8-bit Pulse Width Modulation  
output 0  
P4.3  
PWM0  
27  
I/O  
General I/O port pin  
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uPSD3212A, uPSD3212C, uPSD3212CV  
Function  
Signal  
Name  
Port Pin  
Pin No. In/Out  
Basic  
Alternate  
8-bit Pulse Width Modulation  
output 1  
P4.4  
P4.5  
P4.6  
P4.7  
PWM1  
PWM2  
PWM3  
PWM4  
USB–  
25  
23  
19  
18  
8
I/O  
I/O  
I/O  
I/O  
I/O  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
8-bit Pulse Width Modulation  
output 2  
8-bit Pulse Width Modulation  
output 3  
Programmable 8-bit Pulse Width  
modulation output 4  
Pull-up resistor required (2kfor 3V  
devices, 7.5kfor 5V devices)  
V
70  
65  
62  
63  
4
O
O
O
O
O
I
Reference Voltage input for ADC  
READ signal, external bus  
WRITE signal, external bus  
PSEN signal, external bus  
Address Latch signal, external bus  
Active low RESET input  
REF  
RD_  
WR_  
PSEN_  
ALE  
RESET_  
XTAL1  
XTAL2  
68  
48  
49  
35  
34  
I
Oscillator input pin for system clock  
Oscillator output pin for system clock  
General I/O port pin  
O
I/O  
I/O  
PA0  
PA1  
PA2  
PA3  
PA4  
PA5  
PA6  
PA7  
PB0  
PB1  
PB2  
PB3  
PB4  
PB5  
PB6  
PB7  
General I/O port pin  
www.BDTIC.com/ST  
32  
28  
26  
24  
22  
21  
80  
78  
76  
74  
73  
72  
67  
66  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
General I/O port pin  
1. PLD Macro-cell outputs  
2. PLD inputs  
3. Latched Address Out (A0-  
A7)  
4. Peripheral I/O Mode  
1. PLD Macro-cell outputs  
2. PLD inputs  
3. Latched Address Out (A0-  
A7)  
11/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Function  
Signal  
Name  
Port Pin  
Pin No. In/Out  
Basic  
Alternate  
JTAG TMS  
JTAG TCK  
20  
16  
15  
14  
9
I
JTAG pin  
JTAG pin  
I
1. PLD Macro-cell outputs  
2. PLD inputs  
V
PC2  
PC3  
PC4  
I/O  
I/O  
I/O  
I
General I/O port pin  
General I/O port pin  
General I/O port pin  
JTAG pin  
STBY  
3. SRAM stand by voltage in-  
TSTAT  
TERR_  
put (V  
)
STBY  
4. SRAM battery-on indicator  
(PC4)  
5. JTAG pins are dedicated  
JTAG TDI  
JTAG TDO  
7
pins  
6
O
JTAG pin  
PC7  
PD1  
5
I/O  
General I/O port pin  
1. PLD I/O  
2. Clock input to PLD and APD  
CLKIN  
3
1
I/O  
I/O  
General I/O port pin  
General I/O port pin  
1. PLD I/O  
2. Chip select to PSD Module  
PD2  
Vcc  
Vcc  
12  
50  
13  
29  
69  
10  
11  
GND  
GND  
GND  
USB+  
NC  
NC  
NC  
www.BDTIC.com/ST  
17  
71  
52-PIN PACKAGE I/O PORT  
The 52-pin package members of the uPSD321x  
Devices have the same port pins as those of the  
80-pin package except:  
Port A (PA0-PA7)  
Port D (PD2)  
Bus control signal (RD,WR,PSEN,ALE)  
Port 0 (P0.0-P0.7, external address/data bus  
AD0-AD7)  
Pin 5 requires a pull-up resistor (2kfor 3V  
devices, 7.5kfor 5V devices) for all devices.  
Port 2 (P2.0-P2.3, external address bus A8-  
A11)  
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uPSD3212A, uPSD3212C, uPSD3212CV  
ARCHITECTURE OVERVIEW  
Memory Organization  
The uPSD321x Devices’s standard 8032 Core has  
separate 64KB address spaces for Program mem-  
ory and Data Memory. Program memory is where  
the 8032 executes instructions from. Data memory  
is used to hold data variables. Flash memory can  
be mapped in either program or data space. The  
Flash memory consists of two flash memory  
blocks: the main Flash (512Kbit) and the Second-  
ary Flash (128Kbit). Except during flash memory  
programming or update, Flash memory can only  
be read, not written to. A Page Register is used to  
access memory beyond the 64K bytes address  
space. Refer to the PSD Module for details on  
mapping of the Flash memory.  
The 8032 core has two types of data memory (in-  
ternal and external) that can be read and written.  
The internal SRAM consists of 256 bytes, and in-  
cludes the stack area.  
The SFR (Special Function Registers) occupies  
the upper 128 bytes of the internal SRAM, the reg-  
isters can be accessed by Direct addressing only.  
Another 2K bytes resides in the PSD Module that  
can be mapped to any address space defined by  
the user.  
Figure 5. Memory Map and Address Space  
MAIN  
FLASH  
EXT. RAM  
INT. RAM  
SFR  
FF  
SECONDARY  
FLASH  
Indirect  
Addressing  
Direct  
Addressing  
64KB  
2KB  
7F  
Indirect  
16KB  
www.BDTIC.com/ST  
or  
Direct  
Addressing  
0
Internal RAM Space  
(256 Bytes)  
Flash Memory Space  
External RAM Space  
(MOVX)  
AI07425  
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uPSD3212A, uPSD3212C, uPSD3212CV  
Registers  
The 8032 has several registers; these are the Pro-  
gram Counter (PC), Accumulator (A), B Register  
(B), the Stack Pointer (SP), the Program Status  
Word (PSW), General purpose registers (R0 to  
R7), and DPTR (Data Pointer register).  
[Parity Flag, P]. This flag reflects on number of Ac-  
cumulator’s “1.” If the number of Accumulator’s 1  
is odd, P=0. otherwise, P=1. The sum of adding  
Accumulator’s 1 to P is always even.  
R0~R7. General purpose 8-bit registers that are  
Accumulator. The Accumulator is the 8-bit gen-  
eral purpose register, used for data operation such  
as transfer, temporary saving, and conditional  
tests. The Accumulator can be used as a 16-bit  
register with B Register as shown in Figure 6.  
B Register. The B Register is the 8-bit general  
purpose register, used for an arithmetic operation  
such as multiply, division with the Accumulator  
(see Figure 7).  
locked in the lower portion of internal data area.  
Data Pointer Register. Data Pointer Register is  
16-bit wide which consists of two-8bit registers,  
DPH and DPL. This register is used as a data  
pointer for the data transmission with external data  
memory in the PSD Module.  
Figure 6. 8032 MCU Registers  
Stack Pointer. The Stack Pointer Register is 8  
bits wide. It is incremented before data is stored  
during PUSH and CALL executions. While the  
stack may reside anywhere in on-chip RAM, the  
Stack Pointer is initialized to 07h after reset. This  
causes the stack to begin at location 08h (see Fig-  
ure 8).  
Program Counter. The Program Counter is a 16-  
bit wide which consists of two 8-bit registers, PCH  
and PCL. This counter indicates the address of the  
next instruction to be executed. In RESET state,  
the program counter has reset routine address  
(PCH:00h, PCL:00h).  
Accumulator  
B Register  
A
B
Stack Pointer  
SP  
PCL  
Program Counter  
PCH  
Program Status Word  
General Purpose  
Register (Bank0-3)  
PSW  
R0-R7  
DPTR(DPH) DPTR(DPL) Data Pointer Register  
AI06636  
Program Status Word. The Program Status  
Figure 7. Configuration of BA 16-bit Registers  
Word (PSW) contains several bits that reflect the  
www.BDTIC.com/ST  
current state of the CPU and select Internal RAM  
(00h to 1Fh: Bank0 to Bank3). The PSW is de-  
scribed in Figure 9., page 15. It contains the Carry  
Flag, the Auxiliary Carry Flag, the Half Carry (for  
BCD operation), the general purpose flag, the  
Register Bank Select Flags, the Overflow Flag,  
and Parity Flag.  
B
B
A
A
Two 8-bit Registers can be used as a "BA" 16-bit Registers  
[Carry Flag, CY]. This flag stores any carry or not  
borrow from the ALU of CPU after an arithmetic  
operation and is also changed by the Shift Instruc-  
tion or Rotate Instruction.  
AI06637  
[Auxiliary Carry Flag, AC]. After operation, this is  
set when there is a carry from Bit 3 of ALU or there  
is no borrow from Bit 4 of ALU.  
Figure 8. Stack Pointer  
Stack Area (30h-FFh)  
[Register Bank Select Flags, RS0, RS1]. This flags  
Bit 15  
Bit 8 Bit 7  
Bit 0  
select one of  
four bank(00~07H:bank0,  
00h  
SP  
08~0Fh:bank1, 10~17h:bank2, 17~1Fh:bank3) in  
Internal RAM.  
00h-FFh  
Hardware Fixed  
[Overflow Flag, OV]. This flag is set to '1' when an  
overflow occurs as the result of an arithmetic oper-  
ation involving signs. An overflow occurs when the  
result of an addition or subtraction exceeds +127  
(7Fh) or -128 (80h). The CLRV instruction clears  
the overflow flag. There is no set instruction. When  
the BIT instruction is executed, Bit 6 of memory is  
copied to this flag.  
SP (Stack Pointer) could be in 00h-FFh  
AI06638  
14/163  
 
       
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 9. PSW (Program Status Word) Register  
MSB  
LSB  
CY AC FO RS1 RS0 OV  
P
Reset Value 00h  
Parity Flag  
PSW  
Carry Flag  
Auxillary Carry Flag  
Bit not assigned  
Overflow Flag  
General Purpose Flag  
Register Bank Select Flags  
(to select Bank0-3)  
AI06639  
Program Memory  
RAM  
The program memory consists of two Flash mem-  
ory: 64KByte Main Flash and 16KByte of Second-  
ary Flash. The Flash memory can be mapped to  
any address space as defined by the user in the  
PSDsoft Tool. It can also be mapped to Data  
memory space during Flash memory update or  
programming.  
Four register banks, each 8 registers wide, occupy  
locations 0 through 31 in the lower RAM area.  
Only one of these banks may be enabled at a time.  
The next 16 bytes, locations 32 through 47, con-  
tain 128 directly addressable bit locations. The  
stack depth is only limited by the available internal  
RAM space of 256 bytes.  
After reset, the CPU begins execution from loca-  
tion 0000h. As shown in Figure 10, each interrupt  
is assigned a fixed location in Program Memory.  
The interrupt causes the CPU to jump to that loca-  
tion, where it commences execution of the service  
routine. External Interrupt 0, for example, is as-  
signed to location 0003h. If External Interrupt 0 is  
going to be used, its service routine must begin at  
XRAM-PSD  
The 2K bytes of XRAM-PSD resides in the PSD  
Module and can be mapped to any address space  
through the DPLD (Decoding PLD) as defined by  
the user in PSDsoft Development tool. The XRAM-  
PSD has a battery backup feature that allow the  
data to be retained in the event of a power lost.  
The battery is connected to the Port C PC2 pin.  
This pin must be configured in PSDSoft to be bat-  
tery back-up.  
www.BDTIC.com/ST  
location 0003h. If the interrupt is not going to be  
used, its service location is available as general  
purpose Program Memory.  
The interrupt service locations are spaced at 8-  
byte intervals: 0003h for External Interrupt 0,  
000Bh for Timer 0, 0013h for External Interrupt 1,  
001Bh for Timer 1 and so forth. If an interrupt ser-  
vice routine is short enough (as is often the case  
in control applications), it can reside entirely within  
that 8-byte interval (see Figure 10). Longer service  
routines can use a jump instruction to skip over  
subsequent interrupt locations, if other interrupts  
are in use.  
Figure 10. Interrupt Location of Program  
Memory  
008Bh  
Interrupt  
Location  
0013h  
8 Bytes  
000Bh  
0003h  
Data memory  
The internal data memory is divided into four phys-  
ically separated blocks: 256 bytes of internal RAM,  
128 bytes of Special Function Registers (SFRs)  
areas and 2K bytes (XRAM-PSD) in the PSD Mod-  
ule.  
Reset  
0000h  
AI06640  
15/163  
 
           
uPSD3212A, uPSD3212C, uPSD3212CV  
SFR  
Addressing Modes  
The SFRs can only be addressed directly in the  
address range from 80h to FFh. Table  
15., page 28 gives an overview of the Special  
Function Registers. Sixteen address in the SFRs  
space are both-byte and bit-addressable. The bit-  
addressable SFRs are those whose address ends  
in 0h and 8h. The bit addresses in this area are  
80h to FFh.  
The addressing modes in uPSD321x Devices in-  
struction set are as follows  
Direct addressing  
Indirect addressing  
Register addressing  
Register-specific addressing  
Immediate constants addressing  
Indexed addressing  
Table 3. RAM Address  
Byte Address  
(in Hexadecimal)  
Byte Address  
(in Decimal)  
(1) Direct addressing. In a direct addressing the  
operand is specified by an 8-bit address field in the  
instruction. Only internal Data RAM and SFRs  
(80~FFH RAM) can be directly addressed.  
255  
48  
FFh  
30h  
msb  
Example:  
mov A, 3EH ;A <----- RAM[3E]  
Bit Address (Hex)  
lsb  
Figure 11. Direct Addressing  
2Fh 7F 7E 7D 7C 7B 7A 79 78 47  
2Eh 77 76 75 74 73 72 71 70 46  
2Dh 6F 6E 6D 6C 6B 6A 69 68 45  
2Ch 67 66 65 64 63 62 61 60 44  
2Bh 5F 5E 5D 5C 5B 5A 59 58 43  
2Ah 57 56 55 54 53 52 51 50 42  
29h 4F 4E 4D 4C 4B 4A 49 48 41  
Program Memory  
A
3Eh  
04  
AI06641  
www.BDTIC.com/ST  
28h 47 46 45 44 43 42 41 40 40  
27h 3F 3E 3D 3C 3B 3A 39 38 39  
26h 37 36 35 34 33 32 31 30 38  
25h 2F 2E 2D 2C 2B 2A 29 28 37  
24h 27 26 25 24 23 22 21 20 36  
23h 1F 1E 1D 1C 1B 1A 19 18 35  
22h 17 16 15 14 13 12 11 10 34  
21h 0F 0E 0D 0C 0B 0A 09 08 33  
20h 07 06 05 04 03 02 01 00 32  
(2) Indirect addressing. In indirect addressing  
the instruction specifies a register which contains  
the address of the operand. Both internal and ex-  
ternal RAM can be indirectly addressed. The ad-  
dress register for 8-bit addresses can be R0 or R1  
of the selected register bank, or the Stack Pointer.  
The address register for 16-bit addresses can only  
be the 16-bit “data pointer” register, DPTR.  
Example:  
mov @R1, #40 H ;[R1] <-----40H  
Figure 12. Indirect Addressing  
1Fh  
18h  
17h  
10h  
0Fh  
08h  
07h  
00h  
31  
24  
23  
16  
15  
8
Register Bank 3  
Register Bank 2  
Register Bank 1  
Register Bank 0  
Program Memory  
55h  
R1  
40h  
55  
AI06642  
7
0
16/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Arithmetic Instructions  
The arithmetic instructions is listed in Table  
4., page 18. The table indicates the addressing  
modes that can be used with each instruction to  
access the <byte> operand. For example, the  
ADD A, <byte> instruction can be written as:  
(3) Register addressing. The register banks,  
containing registers R0 through R7, can be ac-  
cessed by certain instructions which carry a 3-bit  
register specification within the opcode of the in-  
struction. Instructions that access the registers  
this way are code efficient, since this mode elimi-  
nates an address byte. When the instruction is ex-  
ecuted, one of four banks is selected at execution  
time by the two bank select bits in the PSW.  
ADD a, 7FH (direct addressing)  
ADD A, @R0 (indirect addressing)  
ADD a, R7 (register addressing)  
ADD A, #127 (immediate constant)  
Example:  
mov PSW, #0001000B ; select Bank0  
mov A, #30H  
mov R1, A  
Note: Any byte in the internal Data Memory space  
can be incremented without going through the Ac-  
cumulator.  
One of the INC instructions operates on the 16-bit  
Data Pointer. The Data Pointer is used to generate  
16-bit addresses for external memory, so being  
able to increment it in one 16-bit operations is  
(4) Register-specific addressing. Some  
in-  
structions are specific to a certain register. For ex-  
ample, some instructions always operate on the  
Accumulator, or Data Pointer, etc., so no address  
byte is needed to point it. The opcode itself does  
that.  
a useful feature.  
The MUL AB instruction multiplies the Accumula-  
tor by the data in the B register and puts the 16-bit  
product into the concatenated B and Accumulator  
registers.  
The DIV AB instruction divides the Accumulator by  
the data in the B register and leaves the 8-bit quo-  
tient in the Accumulator, and the 8-bit remainder in  
the B register.  
(5) Immediate constants addressing. The val-  
ue of a constant can follow the opcode in Program  
memory.  
Example:  
mov A, #10H.  
(6) Indexed addressing. Only Program memory  
can be accessed with indexed addressing, and it  
can only be read. This addressing mode is intend-  
ed for reading look-up tables in Program memory.  
A 16-bit base register (either DPTR or PC) points  
to the base of the table, and the Accumulator is set  
up with the table entry number. The address of the  
table entry in Program memory is formed by add-  
ing the Accumulator data to the base pointer (see  
Figure 13).  
In shift operations, dividing a number by 2n shifts  
its “n” bits to the right. Using DIV AB to perform the  
division completes the shift in 4?s and leaves the  
B register holding the bits that were shifted out.  
The DAA instruction is for BCD arithmetic opera-  
tions. In BCD arithmetic, ADD and ADDC instruc-  
tions should always be followed by a DAA  
operation, to ensure that the result is also in BCD.  
www.BDTIC.com/ST  
Example:  
Note: DAA will not convert a binary number to  
BCD. The DAA operation produces a meaningful  
result only as the second step in the addition of  
two BCD bytes.  
movc A, @A+DPTR  
Figure 13. Indexed Addressing  
ACC  
3Ah  
DPTR  
1E73h  
Program Memory  
3Eh  
AI06643  
17/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 4. Arithmetic Instructions  
Addressing Modes  
Mnemonic  
Operation  
Dir.  
X
Ind.  
X
Reg.  
X
Imm  
X
ADD A,<byte>  
ADDC A,<byte>  
SUBB A,<byte>  
INC  
A = A + <byte>  
A = A + <byte> + C  
A = A – <byte> – C  
A = A + 1  
X
X
X
X
X
X
X
X
Accumulator only  
INC <byte>  
INC DPTR  
DEC  
<byte> = <byte> + 1  
DPTR = DPTR + 1  
A = A – 1  
X
X
X
X
Data Pointer only  
Accumulator only  
DEC <byte>  
MUL AB  
<byte> = <byte> – 1  
B:A = B x A  
X
X
Accumulator and B only  
Accumulator and B only  
Accumulator only  
A = Int[ A / B ]  
B = Mod[ A / B ]  
DIV AB  
DA A  
Decimal Adjust  
Logical Instructions  
Table 5., page 19 shows list of uPSD321x Devic-  
es logical instructions. The instructions that per-  
form Boolean operations (AND, OR, Exclusive  
OR, NOT) on bytes perform the operation on a bit-  
by-bit basis. That is, if the Accumulator contains  
00110101B and byte contains 01010011B, then:  
If the operation is in response to an interrupt, not  
using the Accumulator saves the time and effort to  
push it onto the stack in the service routine.  
The Rotate instructions (RL A, RLC A, etc.) shift  
the Accumulator 1 bit to the left or right. For a left  
rotation, the MSB rolls into the LSB position. For a  
right rotation, the LSB rolls into the MSB position.  
www.BDTIC.com/ST  
ANL A, <byte>  
will leave the Accumulator holding 00010001B.  
The addressing modes that can be used to access  
the <byte> operand are listed in Table 5.  
The ANL A, <byte> instruction may take any of the  
forms:  
The SWAP A instruction interchanges the high  
and low nibbles within the Accumulator. This is a  
useful operation in BCD manipulations. For exam-  
ple, if the Accumulator contains a binary number  
which is known to be less than 100, it can be quick-  
ly converted to BCD by the following code:  
ANL A,7FH(direct addressing)  
ANL A, @R1 (indirect addressing)  
ANL A,R6 (register addressing)  
ANL A,#53H (immediate constant)  
MOVE B,#10  
DIV AB  
SWAP A  
ADD A,B  
Note: Boolean operations can be performed on  
any byte in the internal Data Memory space with-  
out going through the Accumulator. The XRL  
<byte>, #data instruction, for example, offers a  
quick and easy way to invert port bits, as in  
Dividing the number by 10 leaves the tens digit in  
the low nibble of the Accumulator, and the ones  
digit in the B register. The SWAP and ADD instruc-  
tions move the tens digit to the high nibble of the  
Accumulator, and the ones digit to the low nibble.  
XRL P1, #0FFH.  
18/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 5. Logical Instructions  
Mnemonic  
Addressing Modes  
Operation  
Dir.  
X
Ind.  
Reg.  
Imm  
ANL A,<byte>  
ANL <byte>,A  
ANL <byte>,#data  
ORL A,<byte>  
ORL <byte>,A  
ORL <byte>,#data  
XRL A,<byte>  
XRL <byte>,A  
XRL <byte>,#data  
CRL A  
A = A .AND. <byte>  
A = <byte> .AND. A  
A = <byte> .AND. #data  
A = A .OR. <byte>  
A = <byte> .OR. A  
A = <byte> .OR. #data  
A = A .XOR. <byte>  
A = <byte> .XOR. A  
A = <byte> .XOR. #data  
A = 00h  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Accumulator only  
Accumulator only  
Accumulator only  
Accumulator only  
Accumulator only  
Accumulator only  
Accumulator only  
CPL A  
A = .NOT. A  
RL A  
Rotate A Left 1 bit  
RLC A  
RR A  
Rotate A Left through Carry  
Rotate A Right 1 bit  
RRC A  
Rotate A Right through Carry  
Swap Nibbles in A  
SWAP Awww.BDTIC.com/ST  
19/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Data Transfers  
Internal RAM. Table 6 shows the menu of in-  
structions that are available for moving data  
around within the internal memory spaces, and the  
addressing modes that can be used with each  
one. The MOV <dest>, <src> instruction allows  
data to be transferred between any two internal  
RAM or SFR locations without going through the  
Accumulator. Remember, the Upper 128 bytes of  
data RAM can be accessed only by indirect ad-  
dressing, and SFR space only by direct address-  
ing.  
Note: In uPSD321x Devices, the stack resides in  
on-chip RAM, and grows upwards. The PUSH in-  
struction first increments the Stack Pointer (SP),  
then copies the byte into the stack. PUSH and  
POP use only direct addressing to identify the byte  
being saved or restored, but the stack itself is ac-  
cessed by indirect addressing using the SP regis-  
ter. This means the stack can go into the Upper  
128 bytes of RAM, if they are implemented, but not  
into SFR space.  
The XCH A, <byte> instruction causes the Accu-  
mulator and ad-dressed byte to exchange data.  
The XCHD A, @Ri instruction is similar, but only  
the low nibbles are involved in the exchange. To  
see how XCH and XCHD can be used to facilitate  
data manipulations, consider first the problem of  
shifting and 8-digit BCD number two digits to the  
right. Table 8., page 21 shows how this can be  
done using XCH instructions. To aid in under-  
standing how the code works, the contents of the  
registers that are holding the BCD number and the  
content of the Accumulator are shown alongside  
each instruction to indicate their status after the in-  
struction has been executed.  
After the routine has been executed, the Accumu-  
lator contains the two digits that were shifted out  
on the right. Doing the routine with direct MOVs  
uses 14 code bytes. The same operation with  
XCHs uses only 9 bytes and executes almost  
twice as fast. To right-shift by an odd number of  
digits, a one-digit must be executed. Table  
9., page 21 shows a sample of code that will right-  
shift a BCD number one digit, using the XCHD in-  
struction. Again, the contents of the registers hold-  
ing the number and of the accumulator are shown  
alongside each instruction.  
The Data Transfer instructions include a 16-bit  
MOV that can be used to initialize the Data Pointer  
(DPTR) for look-up tables in Program Memory.  
Table 6. Data Transfer Instructions that Access Internal Data Memory Space  
Addressing Modes  
www.BDTIC.com/ST  
Mnemonic  
Operation  
Dir.  
Ind.  
X
Reg.  
X
Imm  
MOV A,<src>  
MOV <dest>,A  
MOV <dest>,<src>  
MOV DPTR,#data16  
PUSH <src>  
A = <src>  
X
X
<dest> = A  
X
X
X
<dest> = <src>  
X
X
X
X
X
DPTR = 16-bit immediate constant  
INC SP; MOV “@SP”,<src>  
MOV <dest>,”@SP”; DEC SP  
Exchange contents of A and <byte>  
Exchange low nibbles of A and @Ri  
X
X
X
POP <dest>  
XCH A,<byte>  
XCHD A,@Ri  
X
X
X
20/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
First, pointers R1 and R0 are set up to point to the  
two bytes containing the last four BCD digits. Then  
a loop is executed which leaves the last byte, loca-  
tion 2EH, holding the last two digits of the shifted  
number. The pointers are decremented, and the  
loop is repeated for location 2DH. The CJNE in-  
struction (Compare and Jump if Not equal) is a  
loop control that will be described later. The loop  
executed from LOOP to CJNE for R1 = 2EH, 2DH,  
2CH, and 2BH. At that point the digit that was orig-  
inally shifted out on the right has propagated to lo-  
cation 2AH. Since that location should be left with  
0s, the lost digit is moved to the Accumulator.  
Table 7. Shifting a BCD Number Two Digits to  
the Right (using direct MOVs: 14 bytes)  
2A 2B 2C 2D  
2E ACC  
MOV A,2Eh  
00  
12  
12  
12  
12  
00  
34  
34  
34  
12  
12  
56  
56  
34  
34  
34  
78  
56  
56  
56  
56  
78  
78  
78  
78  
78  
MOV 2Eh,2Dh 00  
MOV 2Dh,2Ch 00  
MOV 2Ch,2Bh 00  
MOV 2Bh,#0  
00  
Table 8. Shifting a BCD Number Two Digits to  
the Right (using direct XCHs: 9 bytes)  
2A  
00  
00  
00  
00  
00  
2B  
12  
00  
00  
00  
00  
2C  
34  
34  
12  
12  
12  
2D  
56  
56  
56  
34  
34  
2E ACC  
CLR  
A
78  
78  
78  
78  
56  
00  
12  
34  
56  
78  
XCH A,2Bh  
XCH A,2Ch  
XCH A,2Dh  
XCH A,2Eh  
Table 9. Shifting a BCD Number One Digit to the Right  
2A  
2B  
12  
12  
2C  
2D  
56  
56  
2E  
78  
78  
ACC  
MOV  
R1,#2Eh  
00  
34  
xx  
xx  
MOV  
R0,#2Dh  
00  
34  
www.BDTIC.com/ST  
; loop for R1 = 2Eh  
LOOP:  
MOV  
XCHD  
SWAP  
MOV  
DEC  
A,@R1  
00  
00  
00  
00  
00  
00  
00  
12  
12  
12  
12  
12  
12  
12  
34  
34  
34  
34  
34  
34  
34  
56  
58  
58  
58  
58  
58  
58  
78  
78  
78  
67  
67  
67  
67  
78  
76  
67  
67  
67  
67  
67  
A,@R0  
A
@R1,A  
R1  
DEC  
R0  
CNJE  
R1,#2Ah,LOOP  
; loop for R1 = 2Dh  
; loop for R1 = 2Ch  
; loop for R1 = 2Bh  
00  
00  
08  
12  
18  
01  
38  
23  
23  
45  
45  
45  
67  
67  
67  
45  
23  
01  
CLR  
XCH  
A
08  
00  
01  
01  
23  
23  
45  
45  
67  
67  
00  
08  
A,2Ah  
21/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
External RAM. Table 10 shows a list of the Data  
Transfer instructions that access external Data  
Memory. Only indirect addressing can be used.  
The choice is whether to use a one-byte address,  
@Ri, where Ri can be either R0 or R1 of the se-  
The other MOVC instruction works the same way,  
except the Program Counter (PC) is used as the  
table base, and the table is accessed through a  
subroutine. First the number of the desired en-try  
is loaded into the Accumulator, and the subroutine  
is called:  
lected  
register  
bank,  
or  
a
two-byte  
address, @DTPR.  
MOV A , ENTRY NUMBER  
CALL TABLE  
The subroutine “TABLE” would look like this:  
TABLE: MOVC A , @A+PC  
RET  
The table itself immediately follows the RET (re-  
turn) instruction is Program Memory. This type of  
table can have up to 255 entries, numbered 1  
through 255. Number 0 cannot be used, because  
at the time the MOVC instruction is executed, the  
PC contains the address of the RET instruction.  
An entry numbered 0 would be the RET opcode it-  
self.  
Note: In all external Data RAM accesses, the Ac-  
cumulator is always either the destination or  
source of the data.  
Lookup Tables. Table 11 shows the two instruc-  
tions that are available for reading lookup tables in  
Program Memory. Since these instructions access  
only Program Memory, the lookup tables can only  
be read, not updated.  
The mnemonic is MOVC for “move constant.” The  
first MOVC instruction in Table 11 can accommo-  
date a table of up to 256 entries numbered 0  
through 255. The number of the desired entry is  
loaded into the Accumulator, and the Data Pointer  
is set up to point to the beginning of the table.  
Then:  
MOVC A, @A+DPTR  
copies the desired table entry into the Accumula-  
tor.  
Table 10. Data Transfer Instruction that Access External Data Memory Space  
Address Width  
Mnemonic  
Operation  
8 bits  
MOVX A,@Ri  
READ external RAM @Ri  
www.BDTIC.com/ST  
8 bits  
16 bits  
16 bits  
MOVX @Ri,A  
MOVX A,@DPTR  
MOVX @DPTR,a  
WRITE external RAM @Ri  
READ external RAM @DPTR  
WRITE external RAM @DPTR  
Table 11. Lookup Table READ Instruction  
Mnemonic  
Operation  
MOVC A,@A+DPTR  
MOVC A,@A+PC  
READ program memory at (A+DPTR)  
READ program memory at (A+PC)  
22/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Boolean Instructions  
The uPSD321x Devices contain a complete Bool-  
ean (single-bit) processor. One page of the inter-  
nal RAM contains 128 addressable bits, and the  
SFR space can support up to 128 addressable bits  
as well. All of the port lines are bit-addressable,  
and each one can be treated as a separate single-  
bit port. The instructions that access these bits are  
not just conditional branches, but a complete  
menu of move, set, clear, complement, OR and  
AND instructions. These kinds of bit operations  
are not easily obtained in other architectures with  
any amount of byte-oriented software.  
The instruction set for the Boolean processor is  
shown in Table 12. All bits accesses are by direct  
addressing.  
Bit addresses 00h through 7Fh are in the Lower  
128, and bit addresses 80h through FFh are in  
SFR space.  
addressed bit is set (JC, JB, JBC) or if the ad-  
dressed bit is not set (JNC, JNB). In the above  
case, Bit 2 is being tested, and if bit2 = 0, the CPL  
C instruction is jumped over.  
JBC executes the jump if the addressed bit is set,  
and also clears the bit. Thus a flag can be tested  
and cleared in one operation. All the PSW bits are  
directly addressable, so the Parity Bit, or the gen-  
eral-purpose flags, for example, are also available  
to the bit-test instructions.  
Relative Offset  
The destination address for these jumps is speci-  
fied to the assembler by a label or by an actual ad-  
dress in Program memory. How-ever, the  
destination address assembles to a relative offset  
byte. This is a signed (two’s complement) offset  
byte which is added to the PC in two’s complement  
arithmetic if the jump is executed.  
The range of the jump is therefore -128 to +127  
Program Memory bytes relative to the first byte fol-  
lowing the instruction.  
Note how easily an internal flag can be moved to  
a port pin:  
MOV C,FLAG  
MOV P1.0,C  
In this example, FLAG is the name of any addres-  
sable bit in the Lower 128 or SFR space. An I/O  
line (the LSB of Port 1, in this case) is set or  
cleared depending on whether the Flag Bit is '1' or  
'0.'  
Table 12. Boolean Instructions  
Mnemonic  
ANL C,bit  
ANL C,/bit  
Operation  
C = A .AND. bit  
The Carry Bit in the PSW is used as the single-bit  
C = C .AND. .NOT. bit  
Accumulator of twhe Bwoolewan pr.ocesBsor.DBit inTstruIc- C.com/ST  
ORL C,bit  
ORL C,/bit  
MOV C,bit  
MOV bit,C  
CLR C  
C = A .OR. bit  
C = C .OR. .NOT. bit  
C = bit  
tions that refer to the Carry Bit as C assemble as  
Carry-specific instructions (CLR C, etc.). The Car-  
ry Bit also has a direct address, since it resides in  
the PSW register, which is bit-addressable.  
Note: The Boolean instruction set includes ANL  
and ORL operations, but not the XRL (Exclusive  
OR) operation. An XRL operation is simple to im-  
plement in software. Suppose, for example, it is re-  
quired to form the Exclusive OR of two bits:  
bit = C  
C = 0  
CLR bit  
bit = 0  
SETB C  
SETB bit  
CPL C  
C = 1  
C = bit 1 .XRL. bit2  
The software to do that could be as follows:  
MOV C , bit1  
bit = 1  
C = .NOT. C  
bit = .NOT. bit  
Jump if C =1  
Jump if C = 0  
Jump if bit =1  
Jump if bit = 0  
Jump if bit = 1; CLR bit  
JNB bit2, OVER  
CPL C  
OVER: (continue)  
CPL bit  
JC rel  
First, Bit 1 is moved to the Carry. If bit2 = 0, then  
C now contains the correct result. That is, Bit 1  
.XRL. bit2 = bit1 if bit2 = 0. On the other hand, if  
bit2 = 1, C now contains the complement of the  
correct result. It need only be inverted (CPL C) to  
complete the operation.  
JNC rel  
JB bit,rel  
JNB bit,rel  
JBC bit,rel  
This code uses the JNB instruction, one of a series  
of bit-test instructions which execute a jump if the  
23/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Jump Instructions  
Table 13 shows the list of unconditional jump in-  
structions. The table lists a single “JMP add” in-  
struction, but in fact there are three SJMP, LJMP,  
and AJMP, which differ in the format of the desti-  
nation address. JMP is a generic mnemonic which  
can be used if the programmer does not care  
which way the jump is en-coded.  
The SJMP instruction encodes the destination ad-  
dress as a relative offset, as described above. The  
instruction is 2 bytes long, consisting of the op-  
code and the relative offset byte. The jump dis-  
tance is limited to a range of -128 to +127 bytes  
relative to the instruction following the SJMP.  
The LJMP instruction encodes the destination ad-  
dress as a 16-bit constant. The instruction is 3  
bytes long, consisting of the opcode and two ad-  
dress bytes. The destination address can be any-  
where in the 64K Program Memory space.  
The AJMP instruction encodes the destination ad-  
dress as an 11-bit constant. The instruction is 2  
bytes long, consisting of the opcode, which itself  
contains 3 of the 11 address bits, followed by an-  
other byte containing the low 8 bits of the destina-  
tion address. When the instruction is executed,  
these 11 bits are simply substituted for the low 11  
bits in the PC. The high 5 bits stay the same.  
Hence the destination has to be within the same  
2K block as the instruction following the AJMP.  
The RL A instruction converts the index number (0  
through 4) to an even number on the range 0  
through 8, because each entry in the jump table is  
2 bytes long:  
JUMP TABLE:  
AJMP CASE 0  
AJMP CASE 1  
AJMP CASE 2  
AJMP CASE 3  
AJMP CASE 4  
Table 13 shows a single “CALL addr” instruction,  
but there are two of them, LCALL and ACALL,  
which differ in the format in which the subroutine  
address is given to the CPU. CALL is a generic  
mnemonic which can be used if the programmer  
does not care which way the address is encoded.  
The LCALL instruction uses the 16-bit address for-  
mat, and the subroutine can be anywhere in the  
64K Program Memory space. The ACALL instruc-  
tion uses the 11-bit format, and the subroutine  
must be in the same 2K block as the instruction fol-  
lowing the ACALL.  
In any case, the programmer specifies the subrou-  
tine address to the assembler in the same way: as  
a label or as a 16-bit constant. The assembler will  
put the address into the correct format for the giv-  
en instructions.  
Subroutines should end with a RET instruction,  
which returns execution to the instruction following  
the CALL.  
In all cases the programmer specifies the destina-  
www.BDTIC.com/ST  
tion address to the assembler in the same way: as  
a label or as a 16-bit constant. The assembler will  
put the destination address into the correct format  
for the given instruction. If the format required by  
the instruction will not support the distance to the  
specified destination address, a “Destination out  
of range” message is written into the List file.  
RETI is used to return from an interrupt service  
routine. The only difference between RET and  
RETI is that RETI tells the interrupt control system  
that the interrupt in progress is done. If there is no  
interrupt in progress at the time RETI is executed,  
then the RETI is functionally identical to RET.  
The JMP @A+DPTR instruction supports case  
jumps. The destination address is computed at ex-  
ecution time as the sum of the 16-bit DPTR regis-  
ter and the Accumulator. Typically. DPTR is set up  
with the address of a jump table. In a 5-way  
branch, for ex-ample, an integer 0 through 4 is  
loaded into the Accumulator. The code to be exe-  
cuted might be as follows:  
Table 13. Unconditional Jump Instructions  
Mnemonic  
JMP addr  
JMP @A+DPTR  
CALL addr  
RET  
Operation  
Jump to addr  
Jump to A+DPTR  
Call Subroutine at addr  
Return from subroutine  
Return from Interrupt  
No operation  
MOV DPTR,#JUMP TABLE  
MOV A,INDEX_NUMBER  
RL A  
JMP @A+DPTR  
RETI  
NOP  
24/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 14 shows the list of conditional jumps avail-  
able to the uPSD321x Devices user. All of these  
jumps specify the destination address by the rela-  
tive offset method, and so are limited to a jump dis-  
tance of -128 to +127 bytes from the instruction  
following the conditional jump instruction. Impor-  
tant to note, however, the user specifies to the as-  
sembler the actual destination address the same  
way as the other jumps: as a label or a 16-bit con-  
stant.  
There is no Zero Bit in the PSW. The JZ and JNZ  
instructions test the Accumulator data for that con-  
dition.  
The DJNZ instruction (Decrement and Jump if Not  
Zero) is for loop control. To execute a loop N  
times, load a counter byte with N and terminate the  
loop with a DJNZ to the beginning of the loop, as  
shown below for N = 10:  
Every time the loop was executed, R1 was decre-  
mented, and the looping was to continue until the  
R1 data reached 2Ah.  
Another application of this instruction is in “greater  
than, less than” comparisons. The two bytes in the  
operand field are taken as unsigned integers. If the  
first is less than the second, then the Carry Bit is  
set (1). If the first is greater than or equal to the  
second, then the Carry Bit is cleared.  
Machine Cycles  
A machine cycle consists of a sequence of six  
states, numbered S1 through S6. Each state time  
lasts for two oscillator periods. Thus, a machine  
cycle takes 12 oscillator periods or 1µs if the oscil-  
lator frequency is 12MHz. Refer to Figure  
Each state is divided into a Phase 1 half and a  
Phase 2 half. State Sequence in uPSD321x Devic-  
es shows that retrieve/execute sequences in  
states and phases for various kinds of instructions.  
MOV COUNTER,#10  
LOOP: (begin loop)  
Normally two program retrievals are generated  
during each machine cycle, even if the instruction  
being executed does not require it. If the instruc-  
tion being executed does not need more code  
bytes, the CPU simply ignores the extra retrieval,  
and the Program Counter is not incremented.  
(end loop)  
DJNZ COUNTER, LOOP  
(continue)  
Execution of a one-cycle instruction (Figure  
14., page 26) begins during State 1 of the machine  
cycle, when the opcode is latched into the Instruc-  
tion Register. A second retrieve occurs during S4  
The CJNE instruction (Compare and Jump if Not  
Equal) can also be used for loop control as in Ta-  
ble 9., page 21. Two bytes are specified in the op-  
erand field of the instruction. The jump is executed  
only if the two bytes are not equal. In the example  
of Table 9., page 21 Shifting a BCD Number One  
Digits to the Right, the two bytes were data in R1  
and the constant 2Ah. The initial data in R1 was  
2Eh.  
of the same machine cycle. Execution is complete  
at the end of State 6 of this machine cycle.  
The MOVX instructions take two machine cycles  
to execute. No program retrieval is generated dur-  
ing the second cycle of a MOVX instruction. This  
is the only time program retrievals are skipped.  
The retrieve/execute sequence for MOVX instruc-  
tion is shown in Figure 14., page 26 (d).  
Table 14. Conditional Jump Instructions  
Addressing Modes  
Mnemonic  
Operation  
Dir.  
Ind.  
Reg.  
Imm  
JZ rel  
Jump if A = 0  
Jump if A 0  
Accumulator only  
Accumulator only  
X
JNZ rel  
DJNZ <byte>,rel  
CJNE A,<byte>,rel  
CJNE <byte>,#data,rel  
Decrement and jump if not zero  
Jump if A <byte>  
X
X
X
Jump if <byte> #data  
X
X
25/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 14. State Sequence in uPSD321x Devices  
S1  
S2  
S3  
S4  
S5  
S6  
S1  
S2  
S3  
S4  
S5  
S6  
Osc.  
(XTAL2)  
p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2  
Read next  
opcode and  
discard  
Read next  
opcode  
Read opcode  
S1  
S2  
S3  
S4  
S5  
S6  
S6  
S6  
a. 1-Byte, 1-Cycle Instruction, e.g. INC A  
Read next  
opcode  
Read 2nd  
Byte  
Read opcode  
S1  
S2  
S3  
S4  
S5  
b. 2-Byte, 1-Cycle Instruction, e.g. ADD A, adrs  
Read next  
opcode and  
discard  
Read next  
opcode and  
discard  
Read next  
opcode and  
discard  
Read next  
opcode  
Read opcode  
S1  
S2  
S3  
S4  
S5  
S1  
S2  
S3  
S4  
S5  
S6  
c. 1-Byte, 2-Cycle Instruction, e.g. INC DPTR  
No Fetch  
No ALE  
No Fetch  
Read next  
opcode and  
discard  
Read next  
opcode  
Read opcode  
(MOVX)  
www.BDTIC.com/ST  
S1  
S2  
S3  
S4  
S5  
S6  
S1  
S2  
S3  
S4  
S5  
S6  
Addr  
Data  
d. 1-Byte, 2-Cycle MOVX Instruction  
Access External Memory  
AI06822  
26/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
uPSD3200 HARDWARE DESCRIPTION  
The uPSD321x Devices has a modular architec-  
ture with two main functional modules: the MCU  
Module and the PSD Module. The MCU Module  
consists of a standard 8032 core, peripherals and  
other system supporting functions. The PSD Mod-  
ule provides configurable Program and Data mem-  
ories to the 8032 CPU core. In addition, it has its  
own set of I/O ports and a PLD with 16 macrocells  
for general logic implementation. Ports A,B,C, and  
D are general purpose programmable I/O ports  
that have a port architecture which is different from  
Ports 0-4 in the MCU Module.  
The PSD Module communicates with the CPU  
Core through the internal address, data bus (A0-  
A15, D0-D7) and control signals (RD_, WR_,  
PSEN_ , ALE, RESET_). The user defines the De-  
coding PLD in the PSDsoft Development Tool and  
can map the resources in the PSD Module to any  
program or data address space.  
Figure 15. uPSD321x Devices Functional Modules  
Port 1, Timers and  
Port 3, UART,  
Dedicated  
USB Pins  
Port 4 PWM  
2
2nd UART and ADC  
Intr, Timers,I C  
Port 3  
Port 1  
I2C  
3 Timer /  
8032 Core  
4
USB  
&
Transceiver  
PWM  
5
Channels  
Reset Logic  
LVD & WDT  
Channel  
2 UARTs  
ADC  
Counters  
256 Byte SRAM  
Interrupt  
MCU MODULE  
Port 0, 2  
Ext. Bus  
8032 Internal Bus  
A0-A15  
RD,PSEN  
WR,ALE  
Reset  
D0-D7  
www.BDTIC.com/ST  
PSD MODULE  
128Kb  
Secondary  
Flash  
Bus  
Interface  
512Kb  
Main Flash  
16Kb  
SRAM  
Page Register  
Decode PLD  
PSD Internal Bus  
VCC, GND,  
JTAG ISP  
CPLD - 16 MACROCELLS  
XTAL  
Port C,  
JTAG, PLD I/O  
and GPIO  
Port A & B, PLD  
I/O and GPIO  
Port D  
GPIO  
Dedicated  
Pins  
AI07426b  
27/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
MCU MODULE DISCRIPTION  
This section provides a detail description of the  
MCU Module system functions and Peripherals,  
including:  
Special Function Registers  
A map of the on-chip memory area called the Spe-  
cial Function Register (SFR) space is shown in Ta-  
ble 15.  
Note: In the SFRs not all of the addresses are oc-  
cupied. Unoccupied addresses are not implement-  
ed on the chip. READ accesses to these  
addresses will in general return random data, and  
WRITE accesses will have no effect. User soft-  
ware should write '0s' to these unimplemented lo-  
cations.  
Special Function Registers  
Timers/Counter  
Interrupts  
PWM  
Supervisory Function (LVD and Watchdog)  
USART  
Power Saving Modes  
2
I C Bus  
On-chip Oscillator  
ADC  
I/O Ports  
Table 15. SFR Memory Map  
F8  
FF  
F7  
(1)  
F0  
E8  
E0  
D8  
D0  
C8  
C0  
B8  
B0  
A8  
A0  
98  
90  
88  
80  
B
(1)  
UIEN  
UCON0  
UCON1  
UCON2  
S2CON  
USTA  
UADR  
UDT1  
S2DAT  
UDR0  
UDT0  
EF  
E7  
DF  
D7  
CF  
C7  
BF  
B7  
AF  
A7  
9F  
97  
UISTA  
(1)  
USCL  
ACC  
S2STA  
S2ADR  
(1)  
PSW  
www.BDTIC.com/ST  
(1)  
T2MOD  
RCAP2L RCAP2H  
TL2  
TH2  
T2CON  
(1)  
P4  
(1)  
IP  
(1)  
PSCL0L  
PSCL0H  
PWM4P  
PWM0  
PSCL1L PSCL1H  
PWM4W  
IPA  
P3  
(1)  
WDKEY  
WDRST  
IE  
(1)  
PWMCON  
SBUF  
PWM1  
SBUF2  
P3SFS  
TL1  
PWM2  
PWM3  
IEA  
P2  
SCON  
SCON2  
(1)  
P1SFS  
TMOD  
SP  
P4SFS  
TH0  
ASCL  
TH1  
ADAT  
ACON  
P1  
(1)  
TL0  
8F  
87  
TCON  
(1)  
DPL  
DPH  
PCON  
P0  
Note: 1. Register can be bit addressing  
28/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 16. List of all SFR  
Bit Register Name  
SFR  
Addr  
Reset  
Value  
Reg Name  
Comments  
7
6
5
4
3
2
1
0
80  
81  
82  
83  
87  
P0  
SP  
FF  
07  
Port 0  
Stack Ptr  
DPL  
DPH  
PCON  
00 Data Ptr Low  
00 Data Ptr High  
SMOD  
TF1  
SMOD1 LVREN ADSFINT RCLK1 TCLK1  
PD  
IE0  
IDLE  
IT0  
00  
00  
Power Ctrl  
Timer / Cntr  
Control  
88  
89  
TCON  
TMOD  
TR1  
C/T  
TF0  
M1  
TR0  
M0  
IE1  
IT1  
Timer / Cntr  
Mode Control  
Gate  
Gate  
C/T  
M1  
M0  
00  
8A  
8B  
8C  
8D  
90  
TL0  
TL1  
TH0  
TH1  
P1  
00 Timer 0 Low  
00 Timer 1 Low  
00 Timer 0 High  
00 Timer 1 High  
FF  
00  
Port 1  
Port 1 Select  
Register  
91  
93  
94  
P1SFS  
P3SFS  
P4SFS  
P1S7  
P3S7  
P4S7  
P1S6  
P3S6  
P4S6  
P1S5  
P4S5  
P1S4  
P4S4  
Port 3 Select  
Register  
00  
00  
Port 4 Select  
Register  
P4S3  
P4S2  
P4S1  
P4S0  
8-bit  
00 Prescaler for  
ADC clock  
www.BDTIC.com/ST  
95  
ASCL  
ADC Data  
00  
96  
97  
ADAT  
ADAT7  
ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 ADAT1 ADAT0  
Register  
ADC Control  
Register  
ACON  
ADEN  
SM2  
ADS1  
TB8  
ADS0  
RB8  
ADST  
TI  
ADSF  
RI  
00  
Serial Control  
98  
99  
SCON  
SBUF  
SM0  
SM0  
SM1  
SM1  
REN  
REN  
00  
Register  
00 Serial Buffer  
2nd UART  
00  
9A SCON2  
SM2  
TB8  
RB8  
TI  
RI  
Ctrl Register  
2nd UART  
00  
9B  
A0  
SBUF2  
P2  
Serial Buffer  
FF  
00  
Port 2  
PWM Control  
Polarity  
A1 PWMCON PWML  
PWMP PWME CFG4  
CFG3  
CFG2  
CFG1  
CFG0  
PWM0  
A2  
A3  
PWM0  
PWM1  
00 Output Duty  
Cycle  
PWM1  
00 Output Duty  
Cycle  
29/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Bit Register Name  
SFR  
Addr  
Reset  
Value  
Reg Name  
Comments  
7
6
5
4
3
2
1
0
PWM2  
A4  
A5  
PWM2  
00 Output Duty  
Cycle  
PWM3  
00 Output Duty  
Cycle  
PWM3  
Watch Dog  
A6 WDRST  
00  
Reset  
Interrupt  
00  
2
A7  
IEA  
IE  
ES2  
ES  
EI C  
Enable (2nd)  
Interrupt  
A8  
A9  
EA  
-
ET2  
ET1  
EX1  
ET0  
EX0  
00  
Enable  
PWM 4  
Period  
AA PWM4P  
AB PWM4W  
AE WDKEY  
00  
PWM 4 Pulse  
00  
Width  
Watch Dog  
00  
Key Register  
B0  
P3  
FF  
00  
Port 3  
Prescaler 0  
Low (8-bit)  
B1 PSCL0L  
B2 PSCL0H  
B3 PSCL1L  
B4 PSCL1H  
Prescaler 0  
High (8-bit)  
00  
www.BDTIC.com/ST  
Prescaler 1  
Low (8-bit)  
00  
Prescaler 1  
High (8-bit)  
00  
Interrupt  
Priority (2nd)  
B7  
IPA  
PS2  
PS  
PI2C  
PT0  
00  
Interrupt  
Priority  
B8  
C0  
IP  
PT2  
PT1  
PX1  
TR2  
PX0  
00  
FF  
00  
P4  
New Port 4  
Timer 2  
Control  
C8 T2CON  
C9 T2MOD  
CA RCAP2L  
TF2  
EXF2  
RCLK  
TCLK  
EXEN2  
C/T2  
CP/RL2  
DCEN  
00 Timer 2 Mode  
Timer 2  
00  
Reload low  
Timer 2  
00  
CB RCAP2H  
Reload High  
Timer 2 Low  
CC  
CD  
TL2  
TH2  
PSW  
00  
byte  
Timer 2 High  
00  
byte  
Program  
00  
D0  
D1  
CY  
AC  
FO  
RS1  
RS0  
OV  
P
Status Word  
30/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Bit Register Name  
SFR  
Addr  
Reset  
Value  
Reg Name  
Comments  
7
6
5
4
3
2
1
0
2
I C (S2)  
D2 S2SETUP  
00  
Setup  
D4  
D5  
D6  
D7  
D8  
D9  
DA  
DB  
2
I C Bus  
DC S2CON  
CR2  
GC  
EN1  
Stop  
STA  
Intr  
STO  
ADDR  
Bbusy  
AA  
CR1  
CR0  
SLV  
00  
00  
Control Reg  
2
I C Bus  
DD  
DE  
S2STA  
S2DAT  
TX-Md  
Blost  
ACK_R  
Status  
Data Hold  
Register  
00  
00  
2
DF S2ADR  
I C address  
E0  
ACC  
00 Accumulator  
8-bit  
00 Prescaler for  
USB logic  
E1  
USCL  
www.BDTIC.com/ST  
UDT0.7  
USB Endpt1  
Data Xmit  
E6  
E7  
E8  
E9  
UDT1  
UDT0  
UISTA  
UDT1.7  
UDT1.6 UDT1.5 UDT1.4 UDT1.3 UDT1.2 UDT1.1 UDT1.0  
00  
USB Endpt0  
00  
UDT0.6 UDT0.5 UDT0.4 UDT0.3 UDT0.2 UDT0.1 UDT0.0  
Data Xmit  
USBInterrupt  
SUSPND  
RSTF TXD0F RXD0F RXD1F EOPF RESUMF 00  
Status  
USBInterrupt  
Enable  
UIEN SUSPNDIE RSTE RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMIE 00  
USB Endpt0  
Xmit Control  
EA UCON0  
EB UCON1  
EC UCON2  
TSEQ0  
STALL0 TX0E  
RX0E TP0SIZ3 TP0SiZ2 TP0SIZ1 TP0SIZ0 00  
FRESUM TP1SIZ3 TP1SiZ2 TP1SIZ1 TP1SIZ0 00  
USB Endpt1  
Xmit Control  
TSEQ1 EP12SEL  
IN  
USB Control  
Register  
SOUT  
EP2E  
EP1E STALL2 STALL1  
00  
USB Endpt0  
Status  
ED  
EE  
USTA  
RSEQ  
USBEN  
SETUP  
OUT RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 00  
USB Address  
Register  
UADR  
UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0  
00  
USB Endpt0  
Data Recv  
EF  
F0  
UDR0  
B
UDR0.7 UDR0.6 UDR0.5 UDR0.4 UDR0.3 UDR0.2 UDR0.1 UDR0.0  
00  
00  
B Register  
31/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 17. PSD Module Register Address Offset  
CSIOP  
Addr  
Offset  
Bit Register Name  
Reset  
Value  
Register Name  
Comments  
7
6
5
4
3
2
1
0
00  
02  
Data In (Port A)  
Control (Port A)  
Reads Port pins as input  
Configure pin between I/O or Address Out Mode. Bit = 0 selects I/  
O
00  
04  
06  
Data Out (Port A)  
Direction (Port A)  
Latched data for output to Port pins, I/O Output Mode  
Configures Port pin as input or output. Bit = 0 selects input  
00  
00  
Configures Port pin between CMOS, Open Drain or Slew rate. Bit  
= 0 selects CMOS  
08  
0A  
0C  
Drive (Port A)  
00  
Input Macrocell  
(Port A)  
Reads latched value on Input Macrocells  
Enable Out  
(Port A)  
Reads the status of the output enable control to the Port pin driver.  
Bit = 0 indicates pin is in input mode.  
01  
03  
05  
07  
09  
Data In (Port B)  
Control (Port B)  
Data Out (Port B)  
Direction (Port B)  
Drive (Port B)  
00  
00  
00  
00  
Input Macrocell  
(Port B)  
0B  
0D  
Enable Out  
(Port B)  
www.BDTIC.com/ST  
10  
12  
14  
16  
Data In (Port C)  
Data Out (Port C)  
Direction (Port C)  
Drive (Port C)  
00  
00  
00  
Input Macrocell  
(Port C)  
18  
1A  
11  
13  
15  
17  
1B  
20  
Enable Out  
(Port C)  
Only Bit 1 and  
2 are used  
Data In (Port D)  
Data Out (Port D)  
Direction (Port D)  
Drive (Port D)  
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Only Bit 1 and  
2 are used  
00  
00  
00  
Only Bit 1 and  
2 are used  
Only Bit 1 and  
2 are used  
Enable Out  
(Port D)  
Only Bit 1 and  
2 are used  
Output  
Macrocells AB  
32/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
CSIOP  
Addr  
Offset  
Bit Register Name  
Reset  
Value  
Register Name  
Comments  
7
6
5
4
3
2
1
0
Output  
Macrocells BC  
21  
22  
23  
C0  
Mask Macrocells  
AB  
Mask Macrocells  
BC  
Primary Flash  
Protection  
Sec3_ Sec2_ Sec1_ Sec0_  
Bit = 1 sector  
is protected  
Prot  
Prot  
Prot  
Prot  
Security Bit =  
1 device is  
secured  
Secondary Flash Security  
Sec1_ Sec0_  
C2  
B0  
*
*
*
*
*
*
Protection  
_Bit  
Prot  
Prot  
*
PLD  
Mcells array-  
clk  
PLD  
Control PLD  
power  
consumption  
PLD  
Turbo  
APD  
PMMR0  
*
*
00  
enable  
clk  
PLD  
PLD  
PLD  
PLD  
Blocking  
inputs to PLD  
array  
B4  
E0  
PMMR2  
Page  
*
array array array array  
Ale  
*
*
00  
00  
Cntl2 Cntl1 Cntl0  
Page Register  
Configure  
8032 Program  
and Data  
Periph-  
mode  
FL_ Boot_ FL_  
Boot_  
code  
SR_  
code  
E2  
VM  
*
*
data  
data code  
Space  
Note: (Register address = csiop address + address offset; where csiop address is defined by user in PSDsoft)  
* indicates bit is not used and need to set to '0.'  
www.BDTIC.com/ST  
33/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
INTERRUPT SYSTEM  
There are interrupt requests from 10 sources as  
follows (see Figure 16., page 35).  
by EXEN2 and EXF2 Bits in the T2CON  
register.  
2
INT0 External Interrupt  
2nd USART Interrupt  
Timer 0 Interrupt  
I C Interrupt  
INT1 External Interrupt (or ADC Interrupt)  
Timer 1 Interrupt  
USB Interrupt  
USART Interrupt  
Timer 2 Interrupt  
I C Interrupt  
2
The interrupt of the I C is generated by Bit  
INTR in the register S2STA.  
2
This flag is cleared by hardware.  
External Int1  
The INT1 can be either level active or  
transition active depending on Bit IT1 in  
register TCON. The flag that actually  
generates this interrupt is Bit IE1 in TCON.  
When an external interrupt is generated, the  
corresponding request flag is cleared by the  
hardware when the service routine is vectored  
to only if the interrupt was transition activated.  
If the interrupt was level activated then the  
interrupt request flag remains set until the  
requested interrupt is actually generated.  
Then it has to deactivate the request before  
the interrupt service routine is completed, or  
else another interrupt will be generated.  
The ADC can take over the External INT1 to  
generate an interrupt on conversion being  
completed  
External Int0  
The INT0 can be either level-active or  
transition-active depending on Bit IT0 in  
register TCON. The flag that actually  
generates this interrupt is Bit IE0 in TCON.  
When an external interrupt is generated, the  
corresponding request flag is cleared by the  
hardware when the service routine is vectored  
to only if the interrupt was transition activated.  
If the interrupt was level activated then the  
interrupt request flag remains set until the  
requested interrupt is actually generated.  
Then it has to deactivate the request before  
the interrupt service routine is completed, or  
else another interrupt will be generated.  
USB Interrupt  
The USB Interrupt is generated when  
endpoint0 has transmitted a packet or  
received a packet, when endpoint1 or  
www.BDTIC.  
com/ST  
Timer 0 and 1 Interrupts  
endpoint2 has transmitted a packet, when the  
suspend or resume state is detected and  
every EOP received.  
Timer 0 and Timer 1 Interrupts are generated  
by TF0 and TF1 which are set by an overflow  
of their respective Timer/Counter registers  
(except for Timer 0 in Mode 3).  
When the USB Interrupt is generated, the  
corresponding request flag must be cleared by  
software. The interrupt service routine will  
have to check the various USB registers to  
determine the source and clear the  
corresponding flag.  
Please see the dedicated interrupt control  
registers for the USB peripheral for more  
information.  
These flags are cleared by the internal  
hardware when the interrupt is serviced.  
Timer 2 Interrupt  
Timer 2 Interrupt is generated by TF2 which is  
set by an overflow of Timer 2. This flag has to  
be cleared by the software - not by hardware.  
It is also generated by the T2EX signal (Timer  
2 External Interrupt P1.1) which is controlled  
34/163  
 
             
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 16. Interrupt System  
IP / IPA Priority  
Interrupt  
Sources  
IE /  
High  
Low  
INT0  
USART  
Timer  
0
I2C  
INT1  
Timer  
1
USB  
2nd  
USART  
Timer  
2
Global  
Enable  
www.BDTIC.com/ST  
AI07427b  
35/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
USART Interrupt  
The USART Interrupt is generated by RI  
(Receive Interrupt) OR TI (Transmit Interrupt).  
When the USART Interrupt is generated, the  
corresponding request flag must be cleared by  
the software. The interrupt service routine will  
have to check the various USART registers to  
determine the source and clear the  
A low priority interrupt may be interrupted by a  
high priority interrupt level interrupt. A high priority  
interrupt routine cannot be interrupted by any oth-  
er interrupt source. If two interrupts of different pri-  
ority occur simultaneously, the high priority level  
request is serviced. If requests of the same priority  
are received simultaneously, an internal polling  
sequence determines which request is serviced.  
Thus, within each priority level, there is a second  
priority structure determined by the polling se-  
quence.  
corresponding flag.  
Both USART’s are identical, except for the  
additional interrupt controls in the Bit 4 of the  
additional interrupt control registers (A7H,  
B7H).  
Interrupts Enable Structure  
Each interrupt source can be individually enabled  
or disabled by setting or clearing a bit in the inter-  
rupt enable special function register IE and IEA. All  
interrupt source can also be globally disabled by  
the clearing Bit EA in IE (see Table 19). Please  
see Tables 20, 21, 22, and 23 for individual bit de-  
scriptions.  
Interrupt Priority Structure  
Each interrupt source can be assigned one of two  
priority levels. Interrupt priority levels are defined  
by the interrupt priority special function register IP  
and IPA.  
0 = low priority  
1 = high priority  
Table 18. Priority Levels  
Source  
Priority with Level  
Int0  
2nd USART  
Timer 0  
I²C  
0 (highest)  
1
2
www.BDTIC.com/ST  
3
Int1  
4
reserved  
Timer 1  
USB  
5
6
7
8
1st USART  
Timer 2+EXF2  
9 (lowest)  
Table 19. SFR Register  
Bit Register Name  
SFR  
Addr Name  
Reg  
Reset  
Value  
Comments  
7
6
5
4
3
2
1
0
Interrupt  
Enable (2nd)  
2
A7  
A8  
B7  
B8  
IEA  
IE  
ES2  
EUSB  
EX0  
00  
00  
00  
00  
EI C  
ET0  
Interrupt  
Enable  
EA  
ET2  
ES  
PS2  
PS  
ET1  
EX1  
Interrupt  
Priority (2nd)  
2
IPA  
IP  
PUSB  
PX0  
PI C  
Interrupt  
Priority  
PT2  
PT1  
PX1  
PT0  
36/163  
 
         
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 20. Description of the IE Bits.  
Bit  
Symbol  
Function  
Disable all interrupts:  
0: no interrupt with be acknowledged  
1: each interrupt source is individually enabled or disabled by setting or clearing its  
enable bit  
7
EA  
6
5
4
3
2
1
0
Reserved  
ET2  
ES  
Enable Timer 2 Interrupt  
Enable USART Interrupt  
Enable Timer 1 Interrupt  
Enable External Interrupt (Int1)  
Enable Timer 0 Interrupt  
Enable External Interrupt (Int0)  
ET1  
EX1  
ET0  
EX0  
Table 21. Description of the IEA Bits  
Bit  
7
Symbol  
Function  
Not used  
6
Not used  
5
Not used  
4
ES2  
Enable 2nd USART Interrupt  
Not used  
3
2
www.BDTIC.com/ST  
Not used  
1
EI2C  
Enable I²C Interrupt  
Enable USB Interrupt  
0
EUSB  
Table 22. Description of the IP Bits  
Bit  
7
Symbol  
Function  
Reserved  
6
Reserved  
5
PT2  
PS  
Timer 2 Interrupt priority level  
USART Interrupt priority level  
Timer 1 Interrupt priority level  
External Interrupt (Int1) priority level  
Timer 0 Interrupt priority level  
External Interrupt (Int0) priority level  
4
3
PT1  
PX1  
PT0  
PX0  
2
1
0
37/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 23. Description of the IPA Bits  
Bit  
7
Symbol  
Function  
Not used  
6
Not used  
5
Not used  
4
PS2  
2nd USART Interrupt priority level  
Not used  
3
2
Not used  
1
PI2C  
PUSB  
I²C Interrupt priority level  
USB Interrupt priority level  
0
How Interrupts are Handled  
The interrupt flags are sampled at S5P2 of every  
machine cycle. The samples are polled during fol-  
lowing machine cycle. If one of the flags was in a  
set condition at S5P2 of the preceding cycle, the  
polling cycle will find it and the interrupt system will  
generate an LCALL to the appropriate service rou-  
tine, provided this H/W generated LCALL is not  
blocked by any of the following conditions:  
Execution proceeds from that location until the  
RETI instruction is encountered. The RETI instruc-  
tion informs the processor that the interrupt routine  
is no longer in progress, then pops the top two  
bytes from the stack and reloads the Program  
Counter. Execution of the interrupted program  
continues from where it left off.  
Note: A simple RET instruction would also return  
execution to the interrupted program, but it would  
have left the interrupt control system thinking an  
interrupt was still in progress, making future inter-  
rupts impossible.  
An interrupt of equal priority or higher priority  
level is already in progress.  
The current machine cycle is not the final cycle  
in the execution of the instruction in progress.  
The instruction in progress is RETI or any  
access to the interrupt priority or interrupt  
enable registers.  
www.BDTIC.com/ST  
Table 24. Vector Addresses  
Source  
Int0  
Vector Address  
The polling cycle is repeated with each machine  
cycle, and the values polled are the values that  
were present at S5P2 of the previous machine cy-  
cle.  
0003h  
004Bh  
000Bh  
0043h  
0013h  
001Bh  
0033h  
0023h  
002Bh  
2nd USART  
Timer 0  
I²C  
Note: If an interrupt flag is active but being re-  
sponded to for one of the above mentioned condi-  
tions, if the flag is still inactive when the blocking  
condition is removed, the denied interrupt will not  
be serviced. In other words, the fact that the inter-  
rupt flag was once active but not serviced is not re-  
membered. Every polling cycle is new.  
The processor acknowledges an interrupt request  
by executing a hardware generated LCALL to the  
appropriate service routine. The hardware gener-  
ated LCALL pushes the contents of the Program  
Counter on to the stack (but it does not save the  
PSW) and reloads the PC with an address that de-  
pends on the source of the interrupt being vec-  
tored to as shown in Table 24.  
Int1  
Timer 1  
USB  
1st USART  
Timer 2+EXF2  
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uPSD3212A, uPSD3212C, uPSD3212CV  
Power Control Register  
The Idle and Power-down Modes are activated by  
software via the PCON register (see Tables 26  
POWER-SAVING MODE  
Two software selectable modes of reduced power  
consumption are implemented (see Table 25).  
Idle Mode  
The following Functions are Switched Off.  
Idle Mode  
CPU (Halted)  
The instruction that sets PCON.0 is the last in-  
struction executed in the normal operating mode  
before Idle Mode is activated. Once in the Idle  
Mode, the CPU status is preserved in its entirety:  
Stack pointer, Program counter, Program status  
word, Accumulator, RAM and All other registers  
maintain their data during Idle Mode.  
The following Function Remain Active During Idle  
Mode.  
External Interrupts  
Timer 0, Timer 1, Timer 2  
PWM Units  
USART  
There are three ways to terminate the Idle Mode.  
8-bit ADC  
2
Activation of any enabled interrupt will cause  
PCON.0 to be cleared by hardware  
I C Interface  
USB Interface  
terminating Idle mode. The interrupt is  
serviced, and following return from interrupt  
instruction RETI, the next instruction to be  
executed will be the one which follows the  
instruction that wrote a logic '1' to PCON.0.  
Note: Interrupt or RESET terminates the Idle  
Mode.  
Power-Down Mode  
System Clock Halted  
LVD Logic Remains Active  
SRAM contents remains unchanged  
The SFRs retain their value until a RESET is  
asserted  
External hardware reset: the hardware reset is  
required to be active for two machine cycle to  
complete the RESET operation.  
Internal reset: the microcontroller restarts after  
3 machine cycles in all cases.  
Note: The only way to exit Power-down Mode is a  
RESET.  
Power-Down Mode  
www.BDTIC.com/ST  
Table 25. Power-Saving Mode Power Consumption  
2
Mode  
Idle  
Addr/Data  
Maintain Data  
Maintain Data  
Ports1,3,4  
Maintain Data  
Maintain Data  
PWM  
Active  
Disable  
USB  
Active  
Disable  
I C  
Active  
Power-down  
Disable  
Table 26. Pin Status During Idle and Power-down Mode  
Bit Register Name  
SFR  
Reg  
Reset  
Value  
Comments  
Addr Name  
7
6
5
4
3
2
1
0
87 PCON  
SMOD  
SMOD1 LVREN ADSFINT RCLK1 TCLK1  
PD  
IDLE  
00  
Power Ctrl  
39/163  
 
               
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 27. Description of the PCON Bits  
Bit  
7
Symbol  
SMOD  
Function  
Double Baud Data Rate Bit UART  
Double Baud Data Rate Bit 2nd UART  
LVR Disable Bit (active High)  
Enable ADC Interrupt  
6
SMOD1  
LVREN  
5
4
ADSFINT  
(1)  
3
Received Clock Flag (UART 2)  
RCLK1  
(1)  
2
1
0
Transmit Clock Flag (UART 2)  
TCLK1  
PD  
Activate Power-down Mode (High enable)  
Activate Idle Mode (High enable)  
IDL  
Note: 1. See the T2CON register for details of the flag description  
I/O PORTS (MCU MODULE)  
The MCU Module has five ports: Port0, Port1,  
Port2, Port3 and Port 4. (Refer to the PSD Module  
section on I/O ports A,B,C and D). Ports P0 and  
P2 are dedicated for the external address and data  
bus and is not available in the 52-pin package de-  
vices.  
tional special peripheral functions (see Table 28).  
All ports are bi-directional. Pins of which the alter-  
native function is not used may be used as normal  
bi-directional I/O.  
The use of Port1- Port4 pins as alternative func-  
tions are carried out automatically by the  
uPSD321x Devices provided the associated SFR  
Bit is set HIGH.  
Port1 - Port3 are the same as in the standard 8032  
micro-controllers, with the exception of the addi-  
www.BDTIC.com/ST  
Table 28. I/O Port Functions  
Port Name  
Main Function  
Alternate  
Timer 2 - Bits 0,1  
2nd UART - Bits 2,3  
ADC - Bits 4..7  
Port 1  
GPIO  
UART - Bits 0,1  
Interrupt - Bits 2,3  
Timers - Bits 4,5  
Port 3  
Port 4  
GPIO  
GPIO  
2
I C - Bits 6,7  
PWM - Bits 3..7  
40/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
2
The following SFR registers (Tables 29, 30, and  
31) are used to control the mapping of alternate  
functions onto the I/O port bits. Port 1 alternate  
functions are controlled using the P1SFS register,  
except for Timer 2 and the 2nd UART which are  
enabled by their configuration registers. P1.0 to  
P1.3 are default to GPIO after reset.  
Port 3 pins 6 and 7 have been modified from the  
standard 8032. These pins that were used for  
READ and WRITE control signals are now GPIO  
or I C bus pins. The READ and WRITE pins are  
assigned to dedicated pins.  
2
Port 3 (I C) and Port 4 alternate functions are con-  
trolled using the P3SFS and P4SFS Special Func-  
tion Selection registers. After a reset, the I/O pins  
default to GPIO. The alternate function is enabled  
if the corresponding bit in the PXSFS register is  
set to '1.' Other Port 3 alternative functions (UART,  
Interrupt, and Timer/Counter) are enabled by their  
configuration register and do not require setting of  
the bits in R3SFS.  
Table 29. P1SFS (91H)  
7
6
5
4
3
2
1
0
0=Port 1.7  
1=ACH3  
0=Port 1.6  
1=ACH2  
0=Port 1.5  
1=ACH1  
0=Port 1.4  
1=ACH0  
Bits Reserved  
Bits Reserved  
Table 30. P3SFS (93H)  
7
6
5
4
3
2
1
0
0 = Port 3.7 0 = Port 3.6  
1 = SCL  
1 = SDA  
Bits are reserved.  
2
2
from I C unit from I C unit  
Table 31. P4SFS (94H)  
7
6
5
4
3
2
1
0
0=Port 4.7  
1=PWM 4  
0=Port 4.6  
0=Port 4.5  
0=Port 4.4  
0=Port 4.3  
0=Port 4.2  
com/ST  
0=Port 4.1  
0=Port 4.0  
1=PW  
w
w
M 3  
w
1=  
.
PWM  
B
2
D
1=PWM  
T
I
1
C
1=P  
.
WM  
0
41/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
PORT Type and Description  
Figure 17. PORT Type and Description (Part 1)  
In /  
Out  
Symbol  
RESET  
Circuit  
Description  
I
• Schmitt input with internal pull-up  
CMOS compatible interface  
NFC : 400ns  
NFC  
WR, RD,ALE,  
PSEN  
O
Output only  
XTAL1,  
XTAL2  
I
On-chip oscillator  
On-chip feedback resistor  
Stop in the power down mode  
External clock input available  
CMOS compatible interface  
xon  
www.BDTIC.com/ST  
O
Bidirectional I/O port  
PORT0  
I/O  
Schmitt input  
Address Output ( Push-Pull )  
CMOS compatible interface  
AI07438  
42/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 18. PORT Type and Description (Part 2)  
In/  
Out  
Function  
PORT1 <3:0>,  
PORT3,  
PORT4<7:3,1:0>  
Bidirectional I/O port with  
internal pull-ups  
Schmitt input  
I/O  
CMOS compatible interface  
PORT2  
Bidirectional I/O port with  
internal pull-ups  
PORT1 < 7:4 >  
I/O  
Schmitt input  
CMOS compatible interface  
Analog input option  
an_enb  
Bidirectional I/O port with internal  
pull-ups  
I/O  
PORT4.2  
Schmitt input.  
TTL compatible interface  
www.BDTIC.com/ST  
Bidirectional I/O port  
I/O  
USB–, USB+  
Schmitt input  
TTL compatible interface  
+
AI07428b  
43/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
OSCILLATOR  
The oscillator circuit of the uPSD321x Devices is a  
single stage inverting amplifier in a Pierce oscilla-  
tor configuration (see Figure 19). The circuitry be-  
tween XTAL1 and XTAL2 is basically an inverter  
biased to the transfer point. Either a crystal or ce-  
ramic resonator can be used as the feedback ele-  
ment to complete the oscillator circuit. Both are  
operated in parallel resonance.  
XTAL1 is the high gain amplifier input, and XTAL2  
is the output. To drive the uPSD321x Devices ex-  
ternally, XTAL1 is driven from an external source  
and XTAL2 left open-circuit.  
Figure 19. Oscillator  
XTAL1  
XTAL2  
XTAL1  
XTAL2  
8 to 40 MHz  
External Clock  
AI06620  
www.BDTIC.com/ST  
44/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
SUPERVISORY  
There are four ways to invoke a reset and initialize  
the uPSD321x Devices.  
before it is released. On initial power-up the LVR  
is enabled (default). After power-up the LVR can  
be disabled via the LVREN Bit in the PCON Reg-  
ister.  
Note: The LVR logic is still functional in both the  
Idle and Power-down Modes.  
Via the external RESET pin  
Via the internal LVR Block.  
Via Watch Dog timer  
Via USB bus reset signalling  
The reset threshold:  
The RESET mechanism is illustrated in Figure 20.  
5V operation: 4V +/- 0.25V  
3.3V operation: 2.5V +/-0.2V  
Each RESET source will cause an internal reset  
signal active. The CPU responds by executing an  
internal reset and puts the internal registers in a  
defined state. This internal reset is also routed as  
an active low reset input to the PSD Module.  
This logic supports approximately 0.1V of hystere-  
sis and 1µs noise-cancelling delay.  
Watchdog Timer Overflow  
External Reset  
The Watchdog Timer generates an internal reset  
when its 22-bit counter overflows. See Watchdog  
Timer section for details.  
The RESET pin is connected to a Schmitt trigger  
for noise reduction. A RESET is accomplished by  
holding the RESET pin LOW for at least 1ms at  
power up while the oscillator is running. Refer to  
AC spec on other RESET timing requirements.  
USB Reset  
The USB reset is generated by a detection on the  
USB bus RESET signal. A single-end zero on its  
upstream port for 4 to 8 times will set RSTF Bit in  
UISTA register. If Bit 6 (RSTE) of the UIEN Regis-  
ter is set, the detection will also generate the  
RESET signal to reset the CPU and other periph-  
erals in the MCU.  
Low V Voltage Reset  
DD  
An internal reset is generated by the LVR circuit  
when the V drops below the reset threshold. Af-  
DD  
ter V  
reaching back up to the reset threshold,  
DD  
the RESET signal will remain asserted for 10ms  
Figure 20. RESwET Cwonfiwgura.tionBDTIC.com/ST  
Reset  
CPU  
&
PERI.  
Noise  
Cancel  
CPU  
Clock  
Sync  
WDT  
S
LVR  
Q
R
RSTE  
10ms  
Timer  
PSD_RST  
"Active-Low"  
10ms at 40Mhz  
50ms at 8Mhz  
USB Reset  
AI07429b  
45/163  
 
           
uPSD3212A, uPSD3212C, uPSD3212CV  
WATCHDOG TIMER  
The hardware Watchdog Timer (WDT) resets the  
uPSD321x Devices when it overflows. The WDT is  
intended as a recovery method in situations where  
the CPU may be subjected to a software upset. To  
prevent a system reset the timer must be reloaded  
in time by the application software. If the processor  
suffers a hardware/software malfunction, the soft-  
ware will fail to reload the timer. This failure will re-  
sult in a reset upon overflow thus preventing the  
processor running out of control.  
This means the user must reset the WDT at least  
every 4194304 machine cycles (1.258 seconds at  
40MHz). To reset the WDT the user must write a  
value between 00-7EH to the WDRST register.  
The value that is written to the WDRST is loaded  
to the 7MSB of the 22-bit counter. This allows the  
user to pre-loaded the counter to an initial value to  
generate a flexible Watchdog time out period.  
Writing a “00” to WDRST clears the counter.  
The watchdog timer is controlled by the watchdog  
key register, WDKEY. Only pattern 01010101  
(=55H), disables the watchdog timer. The rest of  
pattern combinations will keep the watchdog timer  
enabled. This security key will prevent the watch-  
dog timer from being terminated abnormally when  
the function of the watchdog timer is needed.  
In the Idle Mode the watchdog timer and reset cir-  
cuitry remain active. The WDT consists of a 22-bit  
counter, the Watchdog Timer RESET (WDRST)  
SFR and Watchdog Key Register (WDKEY).  
Since the WDT is automatically enabled while the  
processor is running. the user only needs to be  
concerned with servicing it.  
The 22-bit counter overflows when it reaches  
4194304 (3FFFFFH). The WDT increments once  
every machine cycle.  
In Idle Mode, the oscillator continues to run. To  
prevent the WDT from resetting the processor  
while in Idle, the user should always set up a timer  
that will periodically exit Idle, service the WDT, and  
re-enter Idle Mode.  
Table 32. Watchdog Timer Key Register (WDKEY: 0AEH)  
7
6
5
4
3
2
1
0
WDKEY7  
WDKEY6  
WDKEY5  
WDKEY4  
WDKEY3  
WDKEY2  
WDKEY1  
WDKEY0  
Table 33. Description of the WDKEY Bits  
www.BDTIC.com/ST  
Symbol  
Bit  
Function  
WDKEY7 to Enable or disable Watchdog Timer.  
WDKEY0  
7 to 0  
01010101 (=55h): disable watchdog timer. Others: enable watchdog timer  
46/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Watchdog reset pulse width depends on the clock  
22  
frequency. The reset period is Tf  
x 12 x 2 .  
OSC  
15  
The RESET pulse width is Tf  
x 12 x 2 .  
OSC  
Figure 21. RESET Pulse Width  
Reset pulse width (about 10ms at 40Mhz, about 50ms at 8Mhz)  
Reset period  
(1.258 second at 40Mhz)  
(about 6.291 seconds at 8Mhz)  
AI06823  
Table 34. Watchdog Timer Clear Register (WDRST: 0A6H)  
7
6
5
4
3
2
1
0
Reserved  
WDRST6  
WDRST5  
WDRST4  
WDRST3  
WDRST2  
WDRST1  
WDRST0  
Table 35. Description of the WDRST Bits  
Bit  
Symbol  
Function  
7
Reserved  
To reset Watchdog Timer, write any value beteen 00h and 7Eh to this register.  
WwDRSTw6 tow.BDTIC.com/ST  
6 to 0  
This value is loaded to the 7 most significant bits of the 22-bit counter.  
For example: MOV WDRST,#1EH  
WDRST0  
Note: The Watchdog Timer (WDT) is enabled at power-up or reset and must be served or disabled.  
47/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2)  
The uPSD321x Devices has three 16-bit Timer/  
Counter registers: Timer 0, Timer 1 and Timer 2.  
All of them can be configured to operate either as  
timers or event counters and are compatible with  
standard 8032 architecture.  
In the “Timer” function, the register is incremented  
every machine cycle. Thus, one can think of it as  
counting machine cycles. Since a machine cycle  
consists of 6 CPU clock periods, the count rate is  
1/6 of the CPU clock frequency or 1/12 of Oscilla-  
following the one in which the transition was de-  
tected. Since it takes 2 machine cycles (24 f  
OSC  
clock periods) to recognize a 1-to-0 transition, the  
maximum count rate is 1/24 of the f . There are  
OSC  
no restrictions on the duty cycle of the external in-  
put signal, but to ensure that a given level is sam-  
pled at least once before it changes, it should be  
held for at least one full cycle. In addition to the  
“Timer” or “Counter” selection, Timer 0 and Timer  
1 have four operating modes from which to select.  
tor Frequency (f  
).  
Timer 0 and Timer 1  
OSC  
In the “Counter” function, the register is increment-  
ed in response to a 1-to-0 transition at its corre-  
sponding external input pin, T0 or T1. In this  
function, the external input is sampled during  
S5P2 of every machine cycle. When the samples  
show a high in one cycle and a low in the next cy-  
cle, the count is incremented. The new count value  
appears in the register during S3P1 of the cycle  
The “Timer” or “Counter” function is selected by  
control bits C/T in the Special Function Register  
TMOD. These Timer/Counters have four operat-  
ing modes, which are selected by bit-pairs (M1,  
M0) in TMOD. Modes 0, 1, and 2 are the same for  
Timers/ Counters. Mode 3 is different. The four op-  
erating modes are de-scribed in the following text.  
Table 36. Control Register (TCON)  
7
6
5
4
3
2
1
0
TF1  
TR1  
TF0  
TR0  
IE1  
IT1  
IE0  
IT0  
Table 37. Description of the TCON Bits  
Bit  
Symbol  
Function  
www.BDTIC.com/ST  
Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by  
hardware when processor vectors to interrupt routine  
7
TF1  
6
TR1  
TF0  
TR0  
IE1  
Timer 1 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off  
Timer 0 Overflow Flag. Set by hardier on Timer/Counter overflow. Cleared by hardware  
when processor vectors to interrupt routine  
5
4
Timer 0 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off  
Interrupt 1 Edge Flag. Set by hardware when external interrupt edge detected. Cleared  
when interrupt processed  
3
Interrupt 1 Type Control Bit. Set/cleared by software to specify falling-edge/low-level  
triggered external interrupt  
2
1
0
IT1  
IE0  
IT0  
Interrupt 0 Edge Flag. Set by hardware when external interrupt edge detected. Cleared  
when interrupt processed  
Interrupt 0 Type Control Bit. Set/cleared by software to specify falling-edge/low-level  
triggered external interrupt  
Table 38. TMOD Register (TMOD)  
7
6
5
4
3
2
1
0
Gate  
C/T  
M1  
M0  
Gate  
C/T  
M1  
M0  
48/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 39. Description of the TMOD Bits  
Bit  
Symbol  
Timer  
Function  
Gating control when set. Timer/Counter 1 is enabled only while INT1 pin is High and  
TR1 control pin is set. When cleared, Timer 1 is enabled whenever TR1 control bit is set  
7
Gate  
Timer or Counter selector, cleared for timer operation (input from internal system clock);  
set for counter operation (input from T1 input pin)  
6
5
C/T  
M1  
Timer 1  
(M1,M0)=(0,0): 13-bit Timer/Counter, TH1, with TL1 as 5-bit prescaler  
(M1,M0)=(0,1): 16-bit Timer/Counter. TH1 and TL1 are cascaded. There is no prescaler.  
(M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH1 holds a value which is to be  
reloaded into TL1 each time it overflows  
4
3
M0  
(M1,M0)=(1,1): Timer/Counter 1 stopped  
Gating control when set. Timer/Counter 0 is enabled only while INT0 pin is High and  
TR0 control pin is set. When cleared, Timer 0 is enabled whenever TR0 control bit is set  
Gate  
Timer or Counter selector, cleared for timer operation (input from internal system clock);  
set for counter operation (input from T0 input pin)  
2
1
C/T  
M1  
Timer 0  
(M1,M0)=(0,0): 13-bit Timer/Counter, TH0, with TL0 as 5-bit prescaler  
(M1,M0)=(0,1): 16-bit Timer/Counter. TH0 and TL0 are cascaded. There is no prescaler.  
(M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH0 holds a value which is to be  
reloaded into TL0 each time it overflows  
0
M0  
(M1,M0)=(1,1): TL0 is an 8-bit Timer/Counter controlled by the standard TImer 0 control  
bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits  
www.BDTIC.com/ST  
49/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Mode 0. Putting either Timer into Mode 0 makes  
it look like an 8048 Timer, which is an 8-bit Counter  
with a divide-by-32 prescaler. Figure 22 shows the  
Mode 0 operation as it applies to Timer 1.  
The 13-bit register consists of all 8 bits of TH1 and  
the lower 5 bits of TL1. The upper 3 bits of TL1 are  
indeterminate and should be ignored. Setting the  
run flag does not clear the registers.  
In this mode, the Timer register is configured as a  
13-bit register. As the count rolls over from all '1s'  
to all '0s,' it sets the Timer Interrupt Flag TF1. The  
counted input is enabled to the Timer when TR1 =  
1 and either GATE = 0 or /INT1 = 1. (Setting GATE  
= 1 allows the Timer to be controlled by external in-  
put /INT1, to facilitate pulse width measurements).  
TR1 is a control bit in the Special Function Regis-  
ter TCON (TCON Control Register). GATE is in  
TMOD.  
Mode 0 operation is the same for the Timer 0 as  
for Timer 1. Substitute TR0, TF0, and /INT0 for the  
corresponding Timer 1 signals in Figure 22. There  
are two different GATE Bits, one for Timer 1 and  
one for Timer 0.  
Mode 1. Mode 1 is the same as Mode 0, except  
that the Timer register is being run with all 16 bits.  
Figure 22. Timer/Counter Mode 0: 13-bit Counter  
fOSC  
÷ 12  
C/T = 0  
C/T = 1  
TH1  
(8 bits)  
TL1  
(5 bits)  
TF1  
Interrupt  
T1 pin  
Control  
TR1  
Gate  
INT1 pin  
www.BDTIC.com/ST  
AI06622  
50/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Mode 2. Mode 2 configures the Timer register as  
an 8-bit Counter (TL1) with automatic reload, as  
shown in Figure 23. Overflow from TL1 not only  
sets TF1, but also reloads TL1 with the contents of  
TH1, which is preset by software. The reload  
leaves TH1 unchanged. Mode 2 operation is the  
same for Timer/Counter 0.  
1-to-0 transition at external input T2EX causes the  
current value in the Timer 2 registers, TL2 and  
TH2, to be captured into registers RCAP2L and  
RCAP2H, respectively. In addition, the transition  
at T2EX causes Bit EXF2 in T2CON to be set, and  
EXF2 like TF2 can generate an interrupt. The Cap-  
ture Mode is illustrated in Figure 24., page 53.  
Timer 2  
In the Auto-reload Mode, there are again two op-  
tions, which are selected by bit EXEN2 in T2CON.  
If EXEN2 = 0, then when Timer 2 rolls over it not  
only sets TF2 but also causes the Timer 2 regis-  
ters to be reloaded with the 16-bit value in regis-  
ters RCAP2L and RCAP2H, which are preset by  
software. If EXEN2 = 1, then Timer 2 still does the  
above, but with the added feature that a 1-to-0  
transition at external input T2EX will also trigger  
the 16-bit reload and set EXF2. The Auto-reload  
Mode is illustrated in Standard Serial Interface  
(UART) Figure 25., page 53. The Baud Rate Gen-  
eration Mode is selected by (RCLK, RCLK1) = 1  
and/or (TCLK, TCLK1) = 1. It will be described in  
conjunction with the serial port.  
Like Timer 0 and 1, Timer 2 can operate as either  
an event timer or as an event counter. This is se-  
lected by Bit C/T2 in the special function register  
T2CON (see Table 40). It has three operating  
modes: Capture, Auto-reload, and Baud Rate  
Generator (see Table 41., page 52), which are se-  
lected by bits in the T2CON as shown in Table  
42., page 52. In the Capture Mode there are two  
options which are selected by Bit EXEN2 in  
T2CON. if EXEN2 = 0, then Timer 2 is a 16-bit tim-  
er or counter which upon overflowing sets Bit TF2,  
the Timer 2 overflow bit, which can be used to gen-  
erate an interrupt. If EXEN2 = 1, then Timer 2 still  
does the above, but with the added feature that a  
Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload  
fOSC  
÷ 12  
C/T = 0  
www.BDTIC.com/ST  
TL1  
(8 bits)  
TF1  
Interrupt  
C/T = 1  
T1 pin  
Control  
TR1  
Gate  
INT1 pin  
TH1  
(8 bits)  
AI06623  
Table 40. Timer/Counter 2 Control Register (T2CON)  
7
6
5
4
3
2
1
0
TF2  
EXF2  
RCLK  
TCLK  
EXEN2  
TR2  
C/T2  
CP/RL2  
51/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 41. Timer/Counter 2 Operating Modes  
T2CON  
Input Clock  
External  
T2MOD T2CON P1.1  
RxCLK  
or  
Mode  
Remarks  
CP/  
RL2  
DECN  
EXEN T2EX  
TR2  
Internal  
(P1.0/T2)  
TxCLK  
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
x
x
x
reload upon overflow  
reload trigger (falling edge)  
Down counting  
16-bit  
Auto-  
reload  
MAX  
f
/12  
OSC  
f
/24  
OSC  
0
1
Up counting  
16-bit Timer/Counter  
(only up counting)  
0
0
1
1
1
x
1
1
1
x
x
x
0
1
0
x
x
MAX  
16-bit  
Capture  
f
f
/12  
/12  
OSC  
OSC  
f
f
/24  
OSC  
Capture (TH1,TL2) →  
(RCAP2H,RCAP2L)  
No Overflow Interrupt  
Request (TF2)  
MAX  
Baud Rate  
Generator  
/24  
OSC  
Extra External Interrupt  
(Timer 2)  
1
x
x
x
1
0
x
x
1
x
Off  
x
Timer 2 stops  
Note: = falling edge  
Table 42. Description of the T2CON Bits  
Bit  
Symbol  
Function  
Timer 2 Overflow Flag. Set by a Timer 2 overflow, and must be cleared by software. TF2  
will not be set when either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1  
www.BDTIC.com/ST  
7
TF2  
Timer 2 External Flag set when either a capture or reload is caused by a negative  
transition on T2EX and EXEN2=1. When Timer 2 Interrupt is enabled, EXF2=1 will  
cause the CPU to vector to the Timer 2 Interrupt routine. EXF2 must be cleared by  
6
EXF2  
software  
Receive Clock Flag (UART 1). When set, causes the serial port to use Timer 2 overflow  
pulses for its receive clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be  
used for the receive clock  
(1)  
5
4
3
RCLK  
Transmit Clock Flag (UART 1). When set, causes the serial port to use Timer 2 overflow  
pulses for its transmit clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be  
used for the transmit clock  
(1)  
TCLK  
Timer 2 External Enable Flag. When set, allows a capture or reload to occur as a result  
of a negative transition on T2EX if Timer 2 is not being used to clock the serial port.  
EXEN2=0 causes Time 2 to ignore events at T2EX  
EXEN2  
2
1
TR2  
Start/stop control for Timer 2. A logic 1 starts the timer  
Timer or Counter Select for Timer 2. Cleared for timer operation (input from internal  
C/T2  
system clock, t  
); set for external event counter operation (negative edge triggered)  
CPU  
Capture/Reload Flag. When set, capture will occur on negative transition of T2EX if  
EXEN2=1. When cleared, auto-reload will occur either with TImer 2 overflows, or  
negative transitions of T2EX when EXEN2=1. When either (RCLK, RCLK1)=1 or (TCLK,  
TCLK)=1, this bit is ignored, and timer is forced to auto-reload on Timer 2 overflow  
0
CP/RL2  
Note: 1. The RCLK1 and TCLK1 Bits in the PCON Register control UART 2, and have the same function as RCLK and TCLK.  
52/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 24. Timer 2 in Capture Mode  
fOSC  
÷ 12  
C/T2 = 0  
C/T2 = 1  
TH2  
TF2  
TL2  
(8 bits)  
(8 bits)  
T2 pin  
Control  
TR2  
Timer 2  
Interrupt  
Capture  
RCAP2H  
RCAP2L  
Transition  
Detector  
T2EX pin  
EXP2  
Control  
EXEN2  
AI06625  
Figure 25. Timer 2 in Auto-Reload Mode  
www.BDTIC.com/ST  
÷ 12  
fOSC  
C/T2 = 0  
C/T2 = 1  
TH2  
(8 bits)  
TL2  
(8 bits)  
TF2  
T2 pin  
Control  
TR2  
Timer 2  
Interrupt  
Reload  
RCAP2H  
RCAP2L  
Transition  
Detector  
T2EX pin  
EXP2  
Control  
EXEN2  
AI06626  
53/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Mode 3. Timer 1 in Mode 3 simply holds its count.  
The effect is the same as setting TR1 = 0.  
Mode 3 is provided for applications requiring an  
extra 8-bit timer on the counter. With Timer 0 in  
Mode 3, an uPSD321x Devices can look like it has  
three Timer/Counters. When Timer 0 is in Mode 3,  
Timer 1 can be turned on and off by switching it out  
of and into its own Mode 3, or can still be used by  
the serial port as a baud rate generator, or in fact,  
in any application not requiring an interrupt.  
Timer 0 in Mode 3 establishes TL0 and TH0 as two  
separate counters. The logic for Mode 3 on Timer  
0 is shown in Figure 26. TL0 uses the Timer 0 con-  
trol Bits: C/T, GATE, TR0, INT0, and TF0. TH0 is  
locked into a timer function (counting machine cy-  
cles) and takes over the use of TR1 and TF1 from  
Timer 1. Thus, TH0 now controls the “Timer 1“ In-  
terrupt.  
Figure 26. Timer/Counter Mode 3: Two 8-bit Counters  
fOSC  
÷ 12  
C/T = 0  
C/T = 1  
TL0  
(8 bits)  
TF0  
Interrupt  
T0 pin  
Control  
TR0  
Gate  
INT0 pin  
TH1  
(8 bits)  
fOSC  
TF1  
www.BDTIC.com/ST  
Interrupt  
÷ 12  
Control  
TR1  
AI06624  
54/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
STANDARD SERIAL INTERFACE (UART)  
The uPSD321x Devices provides two standard  
8032 UART serial ports. The first port is connected  
to pin P3.0 (RX) and P3.1 (TX). The second port is  
connected to pin P1.2 (RX) and P1.3(TX). The op-  
eration of the two serial ports are the same and are  
controlled by the SCON and SCON2 registers.  
Mode 3. 11 bits are transmitted (through TxD) or  
received (through RxD): a Start Bit (0), 8 data bits  
(LSB first), a programmable 9th data bit, and a  
Stop Bit (1). In fact, Mode 3 is the same as Mode  
2 in all respects except baud rate. The baud rate  
in Mode 3 is variable.  
The serial port is full duplex, meaning it can trans-  
mit and receive simultaneously. It is also receive-  
buffered, meaning it can commence reception of a  
second byte before a previously received byte has  
been read from the register. (However, if the first  
byte still has not been read by the time reception  
of the second byte is complete, one of the bytes  
will be lost.) The serial port receive and transmit  
registers are both accessed at Special Function  
Register SBUF (or SBUF2 for the second serial  
port). Writing to SBUF loads the transmit register,  
and reading SBUF accesses a physically separate  
receive register.  
In all four modes, transmission is initiated by any  
instruction that uses SBUF as a destination regis-  
ter. Reception is initiated in Mode 0 by the condi-  
tion RI = 0 and REN = 1. Reception is initiated in  
the other modes by the incoming start bit if REN =  
1.  
Multiprocessor Communications  
Modes 2 and 3 have a special provision for multi-  
processor communications. In these modes, 9  
data bits are received. The 9th one goes into RB8.  
Then comes a Stop Bit. The port can be pro-  
grammed such that when the Stop Bit is received,  
the serial port interrupt will be activated only if RB8  
= 1. This feature is enabled by setting Bit SM2 in  
SCON. A way to use this feature in multi-proces-  
sor systems is as follows:  
When the master processor wants to transmit a  
block of data to one of several slaves, it first sends  
out an address byte which identifies the target  
slave. An address byte differs from a data byte in  
that the 9th bit is '1' in an address byte and 0 in a  
data byte. With SM2 = 1, no slave will be interrupt-  
ed by a data byte. An ad-dress byte, however, will  
interrupt all slaves, so that each slave can exam-  
ine the received byte and see if it is being ad-  
dressed. The addressed slave will clear its SM2  
Bit and prepare to receive the data bytes that will  
be coming. The slaves that weren’t being ad-  
dressed leave their SM2s set and go on about  
their business, ignoring the coming data bytes.  
SM2 has no effect in Mode 0, and in Mode 1 can  
be used to check the validity of the Stop Bit. In a  
Mode 1 reception, if SM2 = 1, the Receive Inter-  
rupt will not be activated unless a valid Stop Bit is  
received.  
The serial port can operate in 4 modes:  
Mode 0. Serial data enters and exits through  
RxD. TxD outputs the shift clock. 8 bits are trans-  
mitted/received (LSB first). The baud rate is fixed  
at 1/12 the f  
.
OSC  
Mode 1. 10 bits are transmitted (through TxD) or  
received (through RxD): a start Bit (0), 8 data bits  
(LSB first), and a Stop Bit (1). On receive, the Stop  
Bit goes into RB8 in Special Function Register  
SCON. The baud rate is variable.  
www.BDTIC.com/ST  
Mode 2. 11 bits are transmitted (through TxD) or  
received (through RxD): start Bit (0), 8 data bits  
(LSB first), a programmable 9th data bit, and a  
Stop Bit (1). On Transmit, the 9th data bit (TB8 in  
SCON) can be assigned the value of '0' or '1.' Or,  
for example, the Parity Bit (P, in the PSW) could  
be moved into TB8. On receive, the 9th data bit  
goes into RB8 in Special Function Register SCON,  
while the Stop Bit is ignored. The baud rate is pro-  
grammable to either 1/32 or 1/64 the oscillator fre-  
quency.  
55/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Serial Port Control Register  
The serial port control and status register is the  
Special Function Register SCON (SCON2 for the  
second port), shown in Figure 27. This register  
(see Tables 43 and 44) contains not only the mode  
selection bits, but also the 9th data bit for transmit  
and receive (TB8 and RB8), and the Serial Port In-  
terrupt Bits (TI and RI).  
Figure 27. Serial Port Mode 0, Block Diagram  
Internal Bus  
Write  
to  
SBUF  
RxD  
D
S
P3.0 Alt  
Output  
Function  
Q
SBUF  
CL  
Zero Detector  
Shift  
Start  
Tx Control  
T
Send  
S6  
Tx Clock  
Serial  
Port  
Interrupt  
Shift  
Clock  
TxD  
Receive  
Shift  
R
P3.1 Alt  
Output  
Function  
Rx Clock  
Start  
REN  
R1  
Rx Control  
7
6
5
4
3
2
1
0
RxD  
P3.0 Alt  
Input  
Input Shift Register  
www.BDTIC.com/ST  
Function  
Load  
SBUF  
Shift  
SBUF  
Read  
SBUF  
Internal Bus  
AI06824  
Table 43. Serial Port Control Register (SCON)  
7
6
5
4
3
2
1
0
SM0  
SM1  
SM2  
REN  
TB8  
RB8  
TI  
RI  
56/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 44. Description of the SCON Bits  
Bit  
Symbol  
Function  
7
SM0  
(SM1,SM0)=(0,0): Shift Register. Baud rate = f  
/12  
OSC  
(SM1,SM0)=(1,0): 8-bit UART. Baud rate = variable  
(SM1,SM0)=(0,1): 8-bit UART. Baud rate = f /64 or f  
(SM1,SM0)=(1,1): 8-bit UART. Baud rate = variable  
/32  
OSC  
OSC  
6
SM1  
Enables the multiprocessor communication features in Mode 2 and 3. In Mode 2 or 3, if  
SM2 is set to '1,' RI will not be activated if its received 8th data bit (RB8) is '0.' In Mode 1,  
if SM2=1, RI will not be activated if a valid Stop Bit was not received. In Mode 0, SM2  
should be '0'  
5
SM2  
Enables serial reception. Set by software to enable reception. Clear by software to  
disable reception  
4
3
2
REN  
TB8  
RB8  
The 8th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as  
desired  
In Modes 2 and 3, this bit contains the 8th data bit that was received. In Mode 1, if  
SM2=0, RB8 is the Snap Bit that was received. In Mode 0, RB8 is not used  
Transmit Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode 0, or at  
the beginning of the Stop Bit in the other modes, in any serial transmission. Must be  
cleared by software  
1
0
TI  
Receive Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode 0, or  
halfway through the Stop Bit in the other modes, in any serial reception (except for  
SM2). Must be cleared by software  
RI  
www.BDTIC.com/ST  
57/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Baud Rates. The baud rate in Mode 0 is fixed:  
The Baud Rate Generator Mode is similar to the  
Auto-reload Mode, in that a roll over in TH2 causes  
the Timer 2 registers to be reloaded with the 16-bit  
value in registers RCAP2H and RCAP2L, which  
are preset by software.  
Now, the baud rates in Modes 1 and 3 are deter-  
mined at Timer 2’s overflow rate as follows:  
Mode 0 Baud Rate = f  
/ 12  
OSC  
The baud rate in Mode 2 depends on the value of  
Bit SMOD = 0 (which is the value on reset), the  
baud rate is 1/64 the oscillator frequency. If SMOD  
= 1, the baud rate is 1/32 the oscillator frequency.  
SMOD  
Mode 2 Baud Rate = (2  
/ 64) x f  
OSC  
Mode 1,3 Baud Rate = Timer 2 Overflow Rate / 16  
In the uPSD321x Devices, the baud rates in  
Modes 1 and 3 are determined by the Timer 1  
overflow rate.  
Using Timer 1 to Generate Baud Rates. When  
Timer 1 is used as the baud rate generator, the  
baud rates in Modes 1 and 3 are determined by  
the Timer 1 overflow rate and the value of SMOD  
as follows (see Table 45., page 59):  
The timer can be configured for either “timer” or  
“counter” operation. In the most typical applica-  
tions, it is configured for “timer” operation (C/T2 =  
0). “Timer” operation is a little different for Timer 2  
when it’s being used as a baud rate generator.  
Normally, as a timer it would increment every ma-  
chine cycle (thus at the 1/6 the CPU clock frequen-  
cy). In the case, the baud rate is given by the  
formula:  
Mode 1,3 Baud Rate =  
SMOD  
(2  
/ 32) x (Timer 1 overflow rate)  
Mode 1,3 Baud Rate = f  
(RCAP2H, RCAP2L)]  
/ (32 x [65536 -  
OSC  
The Timer 1 Interrupt should be disabled in this  
application. The Timer itself can be configured for  
either “timer” or “counter” operation, and in any of  
its 3 running modes. In the most typical applica-  
tions, it is configured for “timer” operation, in the  
Auto-reload Mode (high nibble of TMOD = 0010B).  
In that case the baud rate is given by the formula:  
where (RCAP2H, RCAP2L) is the content of  
RC2H and RC2L taken as a 16-bit unsigned inte-  
ger.  
Timer 2 also be used as the Baud Rate Generating  
Mode. This mode is valid only if RCLK + TCLK = 1  
in T2CON or in PCON.  
Note: A roll-over in TH2 does not set TF2, and will  
not generate an interrupt. Therefore, the Timer in-  
terrupt does not have to be disabled when Timer 2  
is in the Baud Rate Generator Mode.  
Note: If EXEN2 is set, a 1-to-0 transition in T2EX  
will set EXF2 but will not cause a reload from  
(RCAP2H, RCAP2L) to (TH2, TL2). Thus when  
Timer 2 is in use as a baud rate generator, T2EX  
can be used as an extra external interrupt, if de-  
sired.  
It should be noted that when Timer 2 is running  
(TR2 = 1) in “timer” function in the Baud Rate Gen-  
erator Mode, one should not try to READ or  
WRITE TH2 or TL2. Under these conditions the  
timer is being incremented every state time, and  
the results of a READ or WRITE may not be accu-  
rate. The RC registers may be read, but should not  
be written to, because a WRITE might overlap a  
reload and cause WRITE and/or reload errors.  
Turn the timer off (clear TR2) before accessing the  
Timer 2 or RC registers, in this case.  
Mode 1,3 Baud Rate =  
SMOD  
(2  
/ 32) x (f  
/ (12 x [256 – (TH1)]))  
OSC  
One can achieve very low baud rates with Timer 1  
by leaving the Timer 1 Interrupt enabled, and con-  
figuring the Timer to run as a 16-bit timer (high nib-  
ble of TMOD = 0001B), and using the Timer 1  
Interrupt to do a 16-bit software reload. Figure  
22., page 50 lists various commonly used baud  
rates and how they can be obtained from Timer 1.  
www.BDTIC.com/ST  
Using Timer/Counter 2 to Generate Baud  
Rates. In the uPSD321x Devices, Timer 2 select-  
ed as the baud rate generator by setting TCLK  
and/or RCLK (see Figure 22., page 50 Timer/  
Counter 2 Control Register (T2CON)).  
Note: The baud rate for transmit and receive can  
be simultaneously different. Setting RCLK and/or  
TCLK puts Timer into its Baud Rate Generator  
Mode.  
The RCLK and TCLK Bits in the T2CON register  
configure UART 1. The RCLK1 and TCLK1 Bits in  
the PCON register configure UART 2.  
58/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 45. Timer 1-Generated Commonly Used Baud Rates  
f
Baud Rate  
SMOD  
Timer 1  
OSC  
C/T  
X
X
0
Mode  
Reload Value  
Mode 0 Max: 1MHz  
12MHz  
12MHz  
X
1
1
1
0
0
0
0
0
0
0
X
X
2
2
2
2
2
2
2
2
1
X
X
Mode 2 Max: 375K  
Modes 1, 3: 62.5K  
12MHz  
FFh  
FDh  
FDh  
FAh  
F4h  
E8h  
1Dh  
72h  
FEEBh  
19.2K  
9.6K  
4.8K  
2.4K  
1.2K  
137.5  
110  
11.059MHz  
11.059MHz  
11.059MHz  
11.059MHz  
11.059MHz  
11.059MHz  
6MHz  
0
0
0
0
0
0
0
110  
12MHz  
0
More About Mode 0. Serial data enters and exits  
through RxD. TxD outputs the shift clock. 8 bits are  
transmitted/received: 8 data bits (LSB first). The  
to the left of the MSB, and all positions to the left  
of that contain zeros. This condition flags the TX  
Control block to do one last shift and then deacti-  
vate SEND and set T1. Both of these actions occur  
at S1P1. Both of these actions occur at S1P1 of  
the 10th machine cycle after “WRITE to SBUF.”  
Reception is initiated by the condition REN = 1 and  
R1 = 0. At S6P2 of the next machine cycle, the RX  
Control unit writes the bits 11111110 to the receive  
shift register, and in the next clock phase activates  
RECEIVE.  
RECEIVE enables SHIFT CLOCK to the alternate  
output function line of TxD. SHIFT CLOCK makes  
transitions at S3P1 and S6P1 of every machine  
cycle in which RECEIVE is active, the contents of  
the receive shift register are shifted to the left one  
position. The value that comes in from the right is  
the value that was sampled at the RxD pin at S5P2  
of the same machine cycle.  
As data bits come in from the right, '1s' shift out to  
the left. When the '0' that was initially loaded into  
the right-most position arrives at the left-most po-  
sition in the shift register, it flags the RX Control  
block to do one last shift and load SBUF. At S1P1  
of the 10th machine cycle after the WRITE to  
SCON that cleared RI, RECEIVE is cleared as RI  
is set.  
baud rate is fixed at 1/12 the f  
.
OSC  
Figure 27., page 56 shows a simplified functional  
diagram of the serial port in Mode 0, and associat-  
ed timing.  
Transmission is initiated by any instruction that  
uses SBUF as a destination register. The “WRITE  
to SBUF” signal at S6P2 also loads a '1' into the  
9th position of the transmit shift register and tells  
the TX Control block to commence a transmission.  
The internal timing is such that one full machine  
cycle will elapse between “WRITE to SBUF” and  
activation of SEND.  
www.BDTIC.com/ST  
SEND enables the output of the shift register to the  
alternate out-put function line of RxD and also en-  
able SHIFT CLOCK to the alternate output func-  
tion line of TxD. SHIFT CLOCK is low during S3,  
S4, and S5 of every machine cycle, and high dur-  
ing S6, S1, and S2. At S6P2 of every machine cy-  
cle in which SEND is active, the contents of the  
transmit shift are shifted to the right one position.  
As data bits shift out to the right, zeros come in  
from the left. When the MSB of the data byte is at  
the output position of the shift register, then the '1'  
that was initially loaded into the 9th position, is just  
59/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 28. Serial Port Mode 0, Waveforms  
Write to SBUF  
S6P2  
Send  
Shift  
Transmit  
Receive  
D0  
S3P1  
D1  
S6P1  
D2  
D3  
D4  
D5  
D6  
D7  
RxD (Data Out)  
TxD (Shift Clock)  
T
Write to SCON  
Clear RI  
RI  
Receive  
Shift  
RxD (Data In)  
TxD (Shift Clock)  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
AI06825  
More About Mode 1. Ten bits are transmitted  
(through TxD), or received (through RxD): a start  
Bit (0), 8 data bits (LSB first). and a Stop Bit (1). On  
receive, the Stop Bit goes into RB8 in SCON. In  
the uPSD321x Devices the baud rate is deter-  
mined by the Timer 1 or Timer 2 overflow rate.  
rate of 16 times whatever baud rate has been es-  
tablished. When a transition is detected, the di-  
vide-by-16 counter is immediately reset, and 1FFH  
is written into the input shift register. Resetting the  
divide-by-16 counter aligns its roll-overs with the  
boundaries of the incoming bit times.  
Figure 29., page 61 shows a simplified functional  
diagram of the serial port in Mode 1, and associat-  
ed timings for transmit receive.  
Transmission is initiated by any instruction that  
uses SBUF as a destination register. The “WRITE  
to SBUF” signal also loads a '1' into the 9th bit po-  
The 16 states of the counter divide each bit time  
into 16ths. At the 7th, 8th, and 9th counter states  
of each bit time, the bit detector samples the value  
of RxD. The value accepted is the value that was  
seen in at least 2 of the 3 samples. This is done for  
noise rejection. If the value accepted during the  
first bit time is not '0,' the receive circuits are reset  
and the unit goes back to looking for an-other 1-to-  
0 transition. This is to provide rejection of false  
start bits. If the start bit proves valid, it is shifted  
into the input shift register, and reception of the re-  
set of the rest of the frame will proceed.  
As data bits come in from the right, '1s' shift out to  
the left. When the start bit arrives at the left-most  
position in the shift register (which in Mode 1 is a  
9-bit register), it flags the RX Control block to do  
one last shift, load SBUF and RB8, and set RI. The  
signal to load SBUF and RB8, and to set RI, will be  
generated if, and only if, the following conditions  
are met at the time the final shift pulse is generat-  
ed:  
www.BDTIC.com/ST  
sition of the transmit shift register and flags the TX  
Control unit that a transmission is requested.  
Transmission actually commences at S1P1 of the  
machine cycle following the next rollover in the di-  
vide-by-16 counter. (Thus, the bit times are syn-  
chronized to the divide-by-16 counter, not to the  
“WRITE to SBUF” signal.)  
The transmission begins with activation of SEND  
which puts the start bit at TxD. One bit time later,  
DATA is activated, which enables the output bit of  
the transmit shift register to TxD. The first shift  
pulse occurs one bit time after that.  
As data bits shift out to the right, zeros are clocked  
in from the left (see Figure 30., page 61). When  
the MSB of the data byte is at the output position  
of the shift register, then the '1' that was initially  
loaded into the 9th position is just to the left of the  
MSB, and all positions to the left of that contain ze-  
ros. This condition flags the TX Control unit to do  
one last shift and then deactivate SEND and set  
TI. This occurs at the 10th divide-by-16 rollover af-  
ter “WRITE to SBUF.”  
1. R1 = 0, and  
2. Either SM2 = 0, or the received Stop Bit = 1.  
If either of these two conditions is not met, the re-  
ceived frame is irretrievably lost. If both conditions  
are met, the Stop Bit goes into RB8, the 8 data bits  
go into SBUF, and RI is activated. At this time,  
whether the above conditions are met or not, the  
unit goes back to looking for a 1-to-0 transition in  
RxD.  
Reception is initiated by a detected 1-to-0 transi-  
tion at RxD. For this purpose RxD is sampled at a  
60/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 29. Serial Port Mode 1, Block Diagram  
Timer1  
Overflow  
Timer2  
Overflow  
Internal Bus  
TB8  
S
Write  
to  
SBUF  
D
TxD  
Q
SBUF  
÷2  
CL  
0
1
Zero Detector  
SMOD  
0
0
1
Shift  
Data  
Start  
TCLK  
Tx Control  
TI  
Send  
÷16  
Tx Clock  
Serial  
1
Port  
Interrupt  
RCLK  
÷16  
Sample  
1-to-0  
Transition  
Detector  
Load SBUF  
Shift  
RI  
Rx Clock  
Start  
Rx Control  
1FFh  
Rx Detector  
Input Shift Register  
Load  
SBUF  
RxD  
Shift  
www.BDTIC.com/ST  
SBUF  
Read  
SBUF  
Internal Bus  
AI06826  
Figure 30. Serial Port Mode 1, Waveforms  
Tx Clock  
Write to SBUF  
S1P1  
Send  
Transmit  
Data  
Shift  
Start Bit  
D0  
D1  
D1  
D2  
D2  
D3  
D3  
D4  
D4  
D5  
D5  
D6  
D6  
D7  
D7  
TxD  
T1  
Stop Bit  
Stop Bit  
÷16 Reset  
Rx Clock  
RxD  
Start Bit  
D0  
Receive  
Bit Detector  
Sample Times  
Shift  
RI  
AI06843  
61/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
More About Modes 2 and 3. Eleven bits are  
transmitted (through TxD), or received (through  
RxD): a Start Bit (0), 8 data bits (LSB first), a pro-  
grammable 9th data bit, and a Stop Bit (1). On  
transmit, the 9th data bit (TB8) can be assigned  
the value of '0' or '1.' On receive, the data bit goes  
into RB8 in SCON. The baud rate is programma-  
ble to either 1/16 or 1/32 the CPU clock frequency  
in Mode 2. Mode 3 may have a variable baud rate  
generated from Timer 1.  
a functional diagram of the serial port in Modes 2  
and 3. The receive portion is exactly the same as  
in Mode 1. The transmit portion differs from Mode  
1 only in the 9th bit of the transmit shift register.  
Transmission is initiated by any instruction that  
uses SBUF as a destination register. The “WRITE  
to SBUF” signal also loads TB8 into the 9th bit po-  
sition of the transmit shift register and flags the TX  
Control unit that a transmission is requested.  
Transmission commences at S1P1 of the machine  
cycle following the next roll-over in the divide-by-  
16 counter. (Thus, the bit times are synchronized  
to the divide-by-16 counter, not to the “WRITE to  
SBUF” signal.)  
activate SEND and set TI. This occurs at the 11th  
divide-by 16 rollover after “WRITE to SUBF.”  
Reception is initiated by a detected 1-to-0 transi-  
tion at RxD. For this purpose RxD is sampled at a  
rate of 16 times whatever baud rate has been es-  
tablished. When a transition is detected, the di-  
vide-by-16 counter is immediately reset, and 1FFH  
is written to the input shift register.  
At the 7th, 8th, and 9th counter states of each bit  
time, the bit detector samples the value of R-D.  
The value accepted is the value that was seen in  
at least 2 of the 3 samples. If the value accepted  
during the first bit time is not '0,' the receive circuits  
are reset and the unit goes back to looking for an-  
other 1-to-0 transition. If the Start Bit proves valid,  
it is shifted into the input shift register, and recep-  
tion of the rest of the frame will proceed.  
As data bits come in from the right, '1s' shift out to  
the left. When the Start Bit arrives at the left-most  
position in the shift register (which in Modes 2 and  
3 is a 9-bit register), it flags the RX Control block  
to do one last shift, load SBUF and RB8, and set  
RI.  
The signal to load SBUF and RB8, and to set RI,  
will be generated if, and only if, the following con-  
ditions are met at the time the final shift pulse is  
generated:  
The transmission begins with activation of SEND,  
which puts the start bit at TxD. One bit time later,  
DATA is activated, which enables the output bit of  
the transmit shift register to TxD. The first shift  
pulse occurs one bit time after that (see Figure  
1. RI = 0, and  
2. Either SM2 = 0, or the received 9th data bit = 1  
If either of these conditions is not met, the received  
frame is irretrievably lost, and RI is not set. If both  
conditions are met, the received 9th data bit goes  
into RB8, and the first 8 data bits go into SBUF.  
One bit time later, whether the above conditions  
were met or not, the unit goes back to looking for  
a 1-to-0 transition at the RxD input.  
shift clocks a '1' (the Stop Bit) into the 9th bit posi-  
tion of the shift register. There-after, only zeros are  
clocked in. Thus, as data bits shift out to the right,  
zeros are clocked in from the left. When TB8 is at  
the out-put position of the shift register, then the  
Stop Bit is just to the left of TB8, and all positions  
to the left of that contain zeros. This condition flags  
the TX Control unit to do one last shift and then de-  
62/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 31. Serial Port Mode 2, Block Diagram  
Phase2 Clock  
Internal Bus  
1/2*f  
OSC  
TB8  
S
Write  
to  
SBUF  
D
TxD  
Q
SBUF  
÷2  
CL  
0
1
Zero Detector  
SMOD  
Shift  
Data  
Start  
Tx Control  
TI  
Send  
÷16  
Tx Clock  
Serial  
Port  
Interrupt  
÷16  
Sample  
1-to-0  
Transition  
Detector  
Load SBUF  
Shift  
RI  
Rx Clock  
Start  
Rx Control  
1FFh  
Rx Detector  
Input Shift Register  
Load  
RxD  
SBUF  
www.BDTIC.com/ST  
Shift  
SBUF  
Read  
SBUF  
Internal Bus  
AI06844  
Figure 32. Serial Port Mode 2, Waveforms  
Tx Clock  
Write to SBUF  
S1P1  
Send  
Data  
Transmit  
Shift  
Start Bit  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
TB8  
TxD  
TI  
Stop Bit  
Stop Bit  
Generator  
÷16 Reset  
Rx Clock  
Start Bit  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
RB8  
RxD  
Stop Bit  
Receive  
Bit Detector  
Sample Times  
Shift  
RI  
AI06845  
63/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 33. Serial Port Mode 3, Block Diagram  
Timer1  
Timer2  
Overflow  
Internal Bus  
SBUF  
Overflow  
TB8  
S
Write  
to  
SBUF  
D
TxD  
Q
÷2  
CL  
0
1
Zero Detector  
SMOD  
0
0
1
Shift  
Data  
Start  
TCLK  
Tx Control  
TI  
Send  
÷16  
Tx Clock  
Serial  
1
Port  
Interrupt  
RCLK  
÷16  
Sample  
1-to-0  
Transition  
Detector  
Load SBUF  
Shift  
RI  
Rx Clock  
Start  
Rx Control  
1FFh  
Rx Detector  
Input Shift Register  
Load  
RxD  
SBUF  
www.BDTIC.com/ST  
Shift  
SBUF  
Read  
SBUF  
Internal Bus  
AI06846  
Figure 34. Serial Port Mode 3, Waveforms  
Tx Clock  
Write to SBUF  
S1P1  
Send  
Data  
Transmit  
Shift  
Start Bit  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
TB8  
TxD  
TI  
Stop Bit  
Stop Bit  
Generator  
÷16 Reset  
Rx Clock  
Start Bit  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
RB8  
RxD  
Stop Bit  
Receive  
Bit Detector  
Sample Times  
Shift  
RI  
AI06847  
64/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
ANALOG-TO-DIGITAL CONVERTOR (ADC)  
The analog to digital (A/D) converter allows con-  
version of an analog input to a corresponding 8-bit  
digital value. The A/D module has four analog in-  
puts, which are multiplexed into one sample and  
hold. The output of the sample and hold is the in-  
put into the converter, which generates the result  
via successive approximation. The analog supply  
matically when A/D conversion is completed,  
cleared when A/D conversion is in process.  
The ASCL should be loaded with a value that re-  
sults in a clock rate of approximately 6MHz for the  
ADC using the following formula (see Table  
ADC clock input = (f  
value +1)  
Where f  
The conversion time for the ADC can be calculat-  
ed as follows:  
ADC Conversion Time = 8 clock * 8bits * (ADC  
Clock) ~= 10.67usec (at 6MHz)  
/ 2) / (Prescaler register  
OSC  
voltage is connected to AVREF of ladder resis-  
tance of A/D module.  
is the MCU clock input frequency  
OSC  
The A/D module has two registers which are the  
control register ACON and A/D result register  
ADAT. The register ACON, shown in Table 46 and  
Table 47., page 66, controls the operation of the  
A/D converter module. To use analog inputs, I/O is  
selected by P1SFS register. Also an 8-bit prescal-  
er ASCL divides the main system clock input down  
to approximately 6MHz clock that is required for  
the ADC logic. Appropriate values need to be load-  
ed into the prescaler based upon the main MCU  
clock frequency prior to use.  
The processing of conversion starts when the  
Start Bit ADST is set to '1.' After one cycle, it is  
cleared by hardware. The register ADAT contains  
the results of the A/D conversion. When conver-  
sion is completed, the result is loaded into the  
ADAT the A/D Conversion Status Bit ADSF is set  
to '1.'  
ADC Interrupt  
The ADSF Bit in the ACON register is set to '1'  
when the A/D conversion is complete. The status  
bit can be driven by the MCU, or it can be config-  
ured to generate a falling edge interrupt when the  
conversion is complete.  
The ADSF Interrupt is enabled by setting the ADS-  
FINT Bit in the PCON register. Once the bit is set,  
the external INT1 Interrupt is disabled and the  
ADSF Interrupt takes over as INT1. INT1 must be  
configured as if it is an edge interrupt input. The  
INP1 pin (p3.3) is available for general I/O func-  
tions, or Timer1 gate control.  
The block diagram of the A/D module is shown in  
Figure 35. The A/D Status Bit ADSF is set auto-  
www.BDTIC.com/ST  
Figure 35. A/D Block Diagram  
Ladder  
Resistor  
Decode  
AVREF  
Conversion  
Complete  
Interrupt  
Input  
MUX  
ACH0  
ACH1  
Successive  
Approximation  
Circuit  
S/H  
ACH2  
ACH3  
ACON  
ADAT  
INTERNAL BUS  
AI06627  
65/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 46. ADC SFR Memory Map  
Bit Register Name  
SFR  
Addr Name  
Reg  
Reset  
Value  
Comments  
7
6
5
4
3
2
1
0
8-bit  
95  
ASCL  
00 Prescaler for  
ADC clock  
ADC Data  
00  
96  
97  
ADAT  
ADAT7  
ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 ADAT1 ADAT0  
Register  
ADC Control  
ACON  
ADEN  
ADS1  
ADS0  
ADST  
ADSF  
00  
Register  
Table 47. Description of the ACON Bits  
Bit  
Symbol  
Function  
7 to 6  
Reserved  
ADEN  
ADC Enable Bit: 0 : ADC shut off and consumes no operating current  
1 : enable ADC  
5
4
Reserved  
ADS1, ADS0 Analog channel select  
0, 0  
0, 1  
1, 0  
1, 1  
Channel0 (ACH0)  
3 to 2  
Channel1 (ACH1)  
Channel2 (ACH2)  
Channel3 (ACH3)  
ADST  
ADC Start Bit:  
0 : force to zero  
1
0
1 : start an ADC; after one cycle, bit is cleared to '0'  
www.BDTIC.com/ST  
ADSF  
ADC Status Bit: 0 : A/D conversion is in process  
1 : A/D conversion is completed, not in process  
Table 48. ADC Clock Input  
MCU Clock Frequency  
Prescaler Register Value  
ADC Clock  
6.7MHz  
40MHz  
36MHz  
24MHz  
12MHz  
2
2
1
0
6MHz  
6MHz  
6MHz  
66/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
PULSE WIDTH MODULATION (PWM)  
The PWM block has the following features:  
fined by the contents of the corresponding Special  
Function Register (PWM 0-3) of a PWM. By load-  
ing the corresponding Special Function Register  
(PWM 0-3) with either 00H or FFH, the PWM out-  
put can be retained at a constant HIGH or LOW  
level respectively (with PWML = 0).  
Four-channel, 8-bit PWM unit with 16-bit  
prescaler  
One-channel, 8-bit unit with programmable  
frequency and pulse width  
PWM Output with programmable polarity  
For each PWM unit, there is a 16-bit Prescaler that  
are used to divide the main system clock to form  
the input clock for the corresponding PWM unit.  
This prescaler is used to define the desired repeti-  
tion rate for the PWM unit. SFR registers B1h -  
B2h are used to hold the 16-bit divisor values.  
4-channel PWM Unit (PWM 0-3)  
The 8-bit counter of a PWM counts module 256  
(i.e., from 0 to 255, inclusive). The value held in  
the 8-bit counter is compared to the contents of the  
Special Function Register (PWM 0-3) of the corre-  
sponding PWM. The polarity of the PWM outputs  
is programmable and selected by the PWML Bit in  
PWMCON register. Provided the contents of a  
PWM 0-3 register is greater than the counter val-  
ue, the corresponding PWM output is set HIGH  
(with PWML = 0). When the contents of this regis-  
ter is less than or equal to the counter value, the  
corresponding PWM output is set LOW (with  
PWML = 0). The pulse-width-ratio is therefore de-  
The repetition frequency of the PWM output is giv-  
en by:  
fPWM = (f  
/ prescaler0) / (2 x 256)  
OSC  
8
And the input clock frequency to the PWM  
counters is = f / 2 / (prescaler data value + 1)  
OSC  
information on how to configure the Port 4 pin as  
PWM output.  
www.BDTIC.com/ST  
67/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 36. Four-Channel 8-bit PWM Block Diagram  
DATA BUS  
8
x 4  
8-bit PWM0-PWM3  
Data Registers  
CPU rd/wr  
x 4  
load  
8-bit PWM0-PWM3  
Comparators Registers  
x 4  
Port4.3  
Port4.4  
Port4.5  
Port4.6  
16-bit Prescaler  
8-bit PWM0-PWM3  
Comparators  
4
CPU rd/wr  
Register  
(B2h,B1h)  
PWMCON bit7 (PWML)  
8
8-bit Counter  
www.BDTIC.com/ST  
16-bit Prescaler  
Counter  
f
OSC/2  
Overflow  
clock  
load  
PWMCON bit5 (PWME)  
AI06647  
68/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 49. PWM SFR Memory Map  
Bit Register Name  
SFR  
Reset Comment  
Reg Name  
Addr  
Value  
s
7
6
5
4
3
2
1
0
PWM  
Control  
Polarity  
A1  
A2  
A3  
A4  
PWMCON PWML PWMP PWME CFG4  
CFG3 CFG2 CFG1  
CFG0  
00  
PWM0  
Output  
Duty Cycle  
PWM0  
PWM1  
PWM2  
00  
00  
00  
PWM1  
Output  
Duty Cycle  
PWM2  
Output  
Duty Cycle  
PWM3  
Output  
Duty Cycle  
A5  
AA  
AB  
PWM3  
PWM4P  
PWM4W  
00  
00  
00  
PWM 4  
Period  
PWM 4  
Pulse  
Width  
Prescaler0  
Low (8-bit)  
B1  
B2  
B3  
B4  
PSCL0L  
PSCL0H  
00  
00  
Prescaler0  
High (8-bit)  
www.BDTIC.com/ST  
Prescaler1  
Low (8-bit)  
PSCL1L  
PSCL1H  
00  
00  
Prescaler1  
High (8-bit)  
PWMCON Register Bit Definition:  
PWML = PWM 0-3 polarity control  
PWMP = PWM 4 polarity control  
PWME = PWM enable (0 = disabled, 1=  
enabled)  
CFG3..CFG0 = PWM 0-3 Output (0 = Open  
Drain; 1 = Push-Pull)  
CFG4 = PWM 4 Output (0 = Open Drain; 1 =  
Push-Pull)  
69/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Programmable Period 8-bit PWM  
The PWM 4 channel can be programmed to pro-  
vide a PWM output with variable pulse width and  
period. The PWM 4 has a 16-bit Prescaler, an 8-  
bit Counter, a Pulse Width Register, and a Period  
Register. The Pulse Width Register defines the  
PWM pulse width time, while the Period Register  
defines the period of the PWM. The input clock to  
the Prescaler is f  
/2. The PWM 4 channel is as-  
OSC  
signed to Port 4.7.  
Figure 37. Programmable PWM 4 Channel Block Diagram  
DATA BUS  
8
8
8
8-bit PWM4P  
CPU RD/WR  
8-bit PWM4W  
Register  
Register  
(Period)  
(Width)  
8
8
8
8-bit PWM4  
Comparator  
Register  
8-bit PWM4  
Comparator  
Register  
Load  
16-bit Prescaler  
CPU RD/WR  
Register  
Port 4.7  
(B4h, B3h)  
PWM4  
Control  
8
8
16  
PWMCON  
Bit 6 (PWMP)  
8-bit PWM4  
Comparator  
8-bit PWM4  
Comparator  
f
/ 2  
OSC  
Match  
16-bit Prescaler  
Counter  
www.BDTIC.com/ST  
8
8
Load  
PWMCON  
Bit 5 (PWME)  
8-bit Counter  
Clock  
Reset  
AI07091  
70/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
PWM 4 Channel Operation  
The 16-bit Prescaler1 divides the input clock  
Counter output. When the content of the counter is  
equal to or greater than the value in the Pulse  
Width Register, it sets the PWM 4 output to low  
(with PWMP Bit = 0). When the Period Register  
equals to the PWM4 Counter, the Counter is  
cleared, and the PWM 4 channel output is set to  
logic 'high' level (beginning of the next PWM  
pulse).  
The Period Register cannot have a value of “00”  
and its content should always be greater than the  
Pulse Width Register.  
The Prescaler1 Register, Pulse Width Register,  
and Period Register can be modified while the  
PWM 4 channel is active. The values of these reg-  
isters are automatically loaded into the Prescaler  
Counter and Comparator Registers when the cur-  
rent PWM 4 period ends.  
(f  
OSC  
/2) to the desired frequency, the resulting  
clock runs the 8-bit Counter of the PWM 4 chan-  
nel. The input clock frequency to the PWM 4  
Counter is:  
f PWM4 = (f  
/2)/(Prescaler1 data value +1)  
OSC  
When the Prescaler1 Register (B4h, B3h) is set to  
data value '0,' the maximum input clock frequency  
to the PWM 4 Counter is f  
as 20MHz.  
/2 and can be as high  
OSC  
The PWM 4 Counter is a free-running, 8-bit  
counter. The output of the counter is compared to  
the Compare Registers, which are loaded with  
data from the Pulse Width Register (PWM4W,  
ABh) and the Period Register (PWM4P, AAh). The  
Pulse Width Register defines the pulse duration or  
the Pulse Width, while the Period Register defines  
the period of the PWM. When the PWM 4 channel  
is enabled, the register values are loaded into the  
Comparator Registers and are compared to the  
The PWMCON Register (Bits 5 and 6) controls the  
enable/disable and polarity of the PWM 4 channel.  
Figure 38. PWM 4 With Programmable Pulse Width and Frequency  
Defined by Period Register  
PWM4  
www.BDTIC.com/ST  
Defined by Pulse  
Width Register  
RESET  
Counter  
Switch Level  
AI07090  
71/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
I2C INTERFACE  
2
The serial port supports the twin line I C-bus, con-  
Slave transmitter  
Slave receiver  
sisting of a data line (SDA1), and a clock line  
(SCL1) as shown in Figure 39. Depending on the  
configuration, the SDA1 and SCL1 lines may re-  
quire pull-up resistors.  
These functions are controlled by the SFRs (see  
Tables 50, 51, and Table 52., page 73):  
S2CON: the control of byte handling and the  
operation of 4 mode.  
S2STA: the contents of its register may also  
be used as a vector to various service  
routines.  
2
These lines also function as I/O port lines if the I C  
bus is not enabled.  
The system is unique because data transport,  
clock generation, address recognition, and bus  
control arbitration are all controlled by hardware.  
S2DAT: data shift register.  
2
The I C serial I/O has complete autonomy in byte  
S2ADR: slave address register. Slave  
address recognition is performed by On-Chip  
H/W.  
handling and operates in 4 modes.  
Master transmitter  
Master receiver  
2
Figure 39. Block Diagram of the I C Bus Serial I/O  
7
0
Slave Address  
Shift Register  
7
0
SDA1  
SCL1  
Arbitration and Sync. Logic  
Bus Clock Generator  
www.BDTIC.com/ST  
7
0
Control Register  
7
0
Status Register  
AI07430  
Table 50. Serial Control Register (S2CON)  
7
6
5
4
3
2
1
0
CR2  
ENII  
STA  
STO  
ADDR  
AA  
CR1  
CR0  
72/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 51. Description of the S2CON Bits  
Bit  
Symbol  
Function  
This bit along with Bits CR1and CR0 determines the serial clock frequency when SIO is  
in the Master Mode.  
7
CR2  
Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are in the high  
impedance state.  
6
5
ENII  
STA  
2
START Flag. When this bit is set, the SIO H/W checks the status of the I C-bus and  
generates a START condition if the bus free. If the bus is busy, the SIO will generate a  
repeated START condition when this bit is set.  
STOP Flag. With this bit set while in Master Mode a STOP condition is generated.  
2
2
When a STOP condition is detected on the I C bus, the I C hardware clears the STO  
Flag.  
Note: This bit have to be set before 1 cycle interrupt period of STOP. That is, if this bit is  
set, STOP condition in Master Mode is generated after 1 cycle interrupt period.  
4
3
STO  
ADDR  
This bit is set when address byte was received. Must be cleared by software.  
Acknowledge enable signal. If this bit is set, an acknowledge (low level to SDA) is  
returned during the acknowledge clock pulse on the SCL line when:  
• Own slave address is received  
2
AA  
• A data byte is received while the device is programmed to be a Master Receiver  
• A data byte is received while the device is a selected Slave Receiver. When this bit is  
reset, no acknowledge is returned.  
SIO release SDA line as high during the acknowledge clock pulse.  
1
0
CR1  
CR0  
These two bits along with the CR2 Bit determine the serial clock frequency when SIO is  
in the Master Mode.  
Table 52. Selection of the Serial Clock Frequency SCL in Master Mode  
www.BDTIC.com/ST  
Bit Rate (kHz) at f  
OSC  
f
Divisor  
CR2  
CR1  
CR0  
OSC  
12MHz  
375  
250  
200  
100  
50  
24MHz  
750  
500  
400  
200  
100  
50  
36MHz  
X
40MHz  
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16  
24  
750  
600  
300  
150  
75  
833  
666  
333  
166  
83  
30  
60  
120  
240  
480  
960  
25  
12.5  
6.25  
25  
37.5  
18.75  
41  
12.5  
20  
73/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Serial Status Register (S2STA)  
S2STA is a “Read-only” register. The contents of  
this register may be used as a vector to a service  
routine. This optimized the response time of the  
3. A data byte has been received or transmitted  
in Master Mode (even if arbitration is lost):  
ack_int  
4. A data byte has been received or transmitted  
as selected slave: ack_int  
5. A stop condition is received as selected slave  
receiver or transmitter: stop_int  
Data Shift Register (S2DAT)  
S2DAT contains the serial data to be transmitted  
or data which has just been received. The MSB  
(Bit 7) is transmitted or received first; that is, data  
shifted from right to left.  
2
software and consequently that of the I C bus. The  
2
status codes for all possible modes of the I C bus  
interface are given Table 54.  
This flag is set, and an interrupt is generated, after  
any of the following events occur:  
1. Own slave address has been received during  
AA = 1: ack_int  
2. The general call address has been received  
while GC(S2ADR.0) = 1 and AA = 1:  
Table 53. Serial Status Register (S2STA)  
7
6
5
4
3
2
1
0
GC  
STOP  
INTR  
TX_MODE  
BBUSY  
BLOST  
/ACK_REP  
SLV  
Table 54. Description of the S2STA Bits  
Bit  
7
Symbol  
GC  
Function  
General Call Flag  
Stop Flag. This bit is set when a STOP condition is received  
6
STOP  
(1,2)  
5
Interrupt Flag. This bit is set when an I²C Interrupt condition is requested  
INTR  
Transmission Mode Flag.  
This bit is set when the I²C is a transmitter; otherwise this bit is reset  
4
3
2
TX_MODE  
www.BDTIC.com/ST  
Bus Busy Flag.  
BBUSY  
This bit is set when the bus is being used by another master; otherwise, this bit is reset  
Bus Lost Flag.  
BLOST  
This bit is set when the master loses the bus contention; otherwise this bit is reset  
Acknowledge Response Flag.  
1
0
/ACK_REP This bit is set when the receiver transmits the not acknowledge signal  
This bit is reset when the receiver transmits the acknowledge signal  
Slave Mode Flag.  
SLV  
This bit is set when the I²C plays role in the Slave Mode; otherwise this bit is reset  
Note: 1. Interrupt Flag Bit (INTR, S2STA Bit 5) is cleared by Hardware as reading S2STA register.  
2
2. I C Interrupt Flag (INTR) can occur in below case.  
Table 55. Data Shift Register (S2DAT)  
7
6
5
4
3
2
1
0
S2DAT7  
S2DAT6  
S2DAT5  
S2DAT4  
S2DAT3  
S2DAT2  
S2DAT1  
S2DAT0  
74/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Address Register (S2ADR)  
2
This 8-bit register may be loaded with the 7-bit  
slave address to which the controller will respond  
when programmed as a slave receive/transmitter.  
The Start/Stop Hold Time Detection and System  
Clock registers (Tables 57 and 58) are included in  
the I C unit to specify the start/stop detection time  
to work with the large range of MCU frequency val-  
ues supported. For example, with a system clock  
of 40MHz.  
Table 56. Address Register (S2ADR)  
7
6
5
4
3
2
1
0
SLA6  
SLA5  
SLA4  
SLA3  
SLA2  
SLA1  
SLA0  
Note: SLA6 to SLA0: Own slave address.  
Table 57. Start /Stop Hold Time Detection Register (S2SETUP)  
Address Register Name Reset Value  
Note  
To control the start/stop hold time detection for the multi-master  
I²C module in Slave Mode  
SFR  
D2h  
S2SETUP  
00h  
Table 58. System Cock of 40MHz  
Number of Sample  
Clock (f /2 – >  
S1SETUP,  
S2SETUP Register  
Value  
Required Start/  
Stop Hold Time  
Note  
OSC  
50ns)  
When Bit 7 (enable bit) = 0, the number of  
sample clock is 1EA (ignore Bit 6 to Bit 0)  
00h  
1EA  
50ns  
80h  
81h  
1EA  
2EA  
50ns  
100ns  
www.BDTIC.com/ST  
82h  
...  
3EA  
...  
150ns  
...  
8Bh  
...  
12EA  
...  
600ns  
...  
Fast Mode I²C Start/Stop hold time specification  
FFh  
128EA  
6000ns  
Table 59. System Clock Setup Examples  
S1SETUP,  
S2SETUP Register  
Number of Sample  
System Clock  
40MHz (f /2 – > 50ns)  
Required Start/Stop Hold Time  
Clock  
Value  
8Bh  
89h  
12 EA  
9 EA  
6 EA  
3 EA  
600ns  
600ns  
600ns  
750ns  
OSC  
30MHz (f  
/2 – > 66.6ns)  
OSC  
20MHz (f  
8MHz (f  
/2 – > 100ns)  
86h  
OSC  
/2 – > 250ns)  
83h  
OSC  
75/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
USB HARDWARE  
The characteristics of USB hardware are as fol-  
lows:  
USB data stream and is able to track jitter and fre-  
quency drift according to the USB specification.  
The SIE also translates the electrical USB signals  
into bytes or signals. Depending upon the device  
USB address and the USB endpoint.  
Address, the USB data is directed to the correct  
endpoint on SIE interface. The data transfer of this  
H/W could be of type control or interrupt.  
Complies with the Universal Serial Bus  
specification Rev. 1.1  
Integrated SIE (Serial Interface Engine), FIFO  
memory and transceiver  
Low speed (1.5Mbit/s) device capability  
Supports control endpoint0 and interrupt  
endpoint1 and 2  
The device’s USB address and the enabling of the  
endpoints are programmable in the SIE configura-  
tion header.  
USB clock input must be 6MHz (requires MCU  
clock frequency to be 12, 24, or 36MHz).  
USB related registers  
The analog front-end is an on-chip generic USB  
transceiver. It is designed to allow voltage levels  
The USB block is controlled via seven registers in  
the memory: (UADR, UCON0, UCON1, UCON2,  
UISTA, UIEN, and USTA).  
Three memory locations on chip which communi-  
cate the USB block are:  
equal to V  
from the standard logic to interface  
DD  
with the physical layer of the Universal Serial Bus.  
It is capable of receiving and transmitting serial  
data at low speed (1.5Mb/s).  
USB endpoint0 data transmit register (UDT0)  
USB endpoint0 data receive register (UDR0)  
USB endpoint1 data transmit register (UDT1)  
The SIE is the digital-front-end of the USB block.  
This module recovers the 1.5MHz clock, detects  
the USB sync word and handles all low-level USB  
protocols and error checking. The bit-clock recov-  
ery circuit recovers the clock from the incoming  
Table 60. USB Address Register (UADR: 0EEh)  
7
6
5
4
3
2
1
0
USBEN  
UADD6  
www.BDTIC.com/ST  
UADD5  
UADD4  
UADD3  
UADD2  
UADD1  
UADD0  
Table 61. Description of the UADR Bits  
Bit  
Symbol  
R/W  
Function  
USB Function Enable Bit.  
When USBEN is clear, the USB module will not respond to any tokens  
from host.  
7
USBEN  
R/W  
RESET clears this bit.  
UADD6 to  
UADD0  
Specify the USB address of the device.  
RESET clears these bits.  
6 to 0  
R/W  
76/163  
 
       
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 62. USB Interrupt Enable Register (UIEN: 0E9h)  
7
6
5
4
3
2
1
0
SUSPNDI  
RSTE  
RSTFIE  
TXD0IE  
RXD0IE  
TXD1IE  
EOPIE  
RESUMI  
Table 63. Description of the UIEN Bits  
Bit  
Symbol  
R/W  
Function  
7
SUSPNDI  
R/W  
Enable SUSPND Interrupt  
Enable USB Reset; also resets the CPU and PSD Modules when bit is  
set to '1.'  
6
RSTE  
R/W  
5
4
3
2
1
0
RSTFIE  
TXD0IE  
RXD0IE  
TXD1IE  
EOPIE  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Enable RSTF (USB Bus Reset Flag) Interrupt  
Enable TXD0 Interrupt  
Enable RXD0 Interrupt  
Enable TXD1 Interrupt  
Enable EOP Interrupt  
RESUMI  
Enable USB Resume Interrupt when it is the Suspend Mode  
www.BDTIC.com/ST  
77/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 64. USB Interrupt Status Register (UISTA: 0E8h)  
7
6
5
4
3
2
1
0
SUSPND  
RSTF  
TXD0F  
RXD0F  
TXD1F  
EOPF  
RESUMF  
Table 65. Description of the UISTA Bits  
Bit  
Symbol  
R/W  
Function  
USB Suspend Mode Flag.  
To save power, this bit should be set if a 3ms constant idle state is  
detected on USB bus. Setting this bit stops the clock to the USB and  
causes the USB module to enter Suspend Mode. Software must clear  
this bit after the Resume flag (RESUMF) is set while this Resume  
Interrupt Flag is serviced  
7
SUSPND  
R/W  
6
5
R
Reserved  
USB Reset Flag.  
This bit is set when a valid RESET signal state is detected on the D+ and  
D- lines. When the RSTE bit in the UIEN Register is set, this reset  
detection will also generate an internal reset signal to reset the CPU and  
other peripherals including the USB module.  
RSTF  
Endpoint0 Data Transmit Flag.  
This bit is set after the data stored in Endpoint 0 transmit buffers has  
been sent and an ACK handshake packet from the host is received.  
Once the next set of data is ready in the transmit buffers, software must  
clear this flag. To enable the next data packet transmission, TX0E must  
also be set. If TXD0F Bit is not cleared, a NAK handshake will be  
returned in the next IN transactions. RESET clears this bit.  
4
3
TXD0F  
R/W  
Endpoint0 Data Receive Flag.  
This bit is set after the USB module has received a data packet and  
responded with ACK handshake packet. Software must clear this flag  
www.BDTIC.com/ST  
RXD0F  
R/W  
after all of the received data has been read. Software must also set  
RX0E Bit to one to enable the next data packet reception. If RXD0F Bit is  
not cleared, a NAK handshake will be returned in the next OUT  
transaction. RESET clears this bit.  
Endpoint1 / Endpoint2 Data Transmit Flag.  
This bit is shared by Endpoints 1 and Endpoints 2. It is set after the data  
stored in the shared Endpoint 1/ Endpoint 2 transmit buffer has been sent  
and an ACK handshake packet from the host is received. Once the next  
set of data is ready in the transmit buffers, software must clear this flag.  
To enable the next data packet transmission, TX1E must also be set. If  
TXD1F Bit is not cleared, a NAK handshake will be returned in the next  
IN transaction. RESET clears this bit.  
2
TXD1F  
R/W  
End of Packet Flag.  
1
0
EOPF  
R/W  
R/W  
This bit is set when a valid End of Packet sequence is detected on the D+  
and D-line. Software must clear this flag. RESET clears this bit.  
Resume Flag.  
This bit is set when USB bus activity is detected while the SUSPND Bit is  
set.  
RESUMF  
Software must clear this flag. RESET clears this bit.  
78/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 66. USB Endpoint0 Transmit Control Register (UCON0: 0EAh)  
7
6
5
4
3
2
1
0
TSEQ0  
STALL0  
TX0E  
RX0E  
TP0SIZ3  
TP0SIZ2  
TP0SIZ1  
TP0SIZ0  
Table 67. Description of the UCON0 Bits  
Bit  
Symbol  
R/W  
Function  
Endpoint0 Data Sequence Bit. (0=DATA0, 1=DATA1)  
This bit determines which type of data packet (DATA0 or DATA1) will be  
sent during the next IN transaction. Toggling of this bit must be controlled  
by software. RESET clears this bit  
7
TSEQ0  
R/W  
Endpoint0 Force Stall Bit.  
This bit causes Endpoint 0 to return a STALL handshake when polled by  
either an IN or OUT token by the USB Host Controller. The USB  
hardware clears this bit when a SETUP token is received. RESET clears  
this bit.  
6
5
STALL0  
TX0E  
R/W  
R/W  
Endpoint0 Transmit Enable.  
This bit enables a transmit to occur when the USB Host Controller sends  
an IN token to Endpoint 0. Software should set this bit when data is ready  
to be transmitted. It must be cleared by software when no more Endpoint  
0 data needs to be transmitted. If this bit is '0' or the TXD0F is set, the  
USB will respond with a NAK handshake to any Endpoint 0 IN tokens.  
RESET clears this bit.  
Endpoint0 receive enable.  
This bit enables a receive to occur when the USB Host Controller sends  
an OUT token to Endpoint 0. Software should set this bit when data is  
ready to be received. It must be cleared by software when data cannot be  
received. If this bit is '0' or the RXD0F is set, the USB will respond with a  
NAK handshake to any Endpoint 0 OUT tokens. RESET clears this bit.  
4
RX0E  
R/W  
www.BDTIC.com/ST  
TP0SIZ3 to  
TP0SIZ0  
3 to 0  
R/W  
The number of transmit data bytes. These bits are cleared by RESET.  
79/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 68. USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh)  
7
6
5
4
3
2
1
0
TSEQ1  
EP12SEL  
TX1E  
FRESUM  
TP1SIZ3  
TP1SIZ2  
TP1SIZ1  
TP1SIZ0  
Table 69. Description of the UCON1 Bits  
Bit  
Symbol  
R/W  
Function  
Endpoint 1/ Endpoint 2 Transmit Data Packet PID. (0=DATA0, 1=DATA1)  
This bit determines which type of data packet (DATA0 or DATA1) will be  
sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.  
Toggling of this bit must be controlled by software. RESET clears this bit.  
7
TSEQ1  
R/W  
Endpoint 1/ Endpoint 2 Transmit Selection. (0=Endpoint 1, 1=Endpoint 2)  
This bit specifies whether the data inside the registers UDT1 are used for  
Endpoint 1 or Endpoint 2. If all the conditions for a successful Endpoint 2  
USB response to a hosts IN token are satisfied (TXD1F=0, TX1E=1,  
STALL2=0, and EP2E=1) except that the EP12SEL Bit is configured for  
Endpoint 1, the USB responds with a NAK handshake packet. RESET  
clears this bit.  
6
EP12SEL  
R/W  
Endpoint1 / Endpoint2 Transmit Enable.  
This bit enables a transmit to occur when the USB Host Controller send  
an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint  
enable bit, EP1E or EP2E Bit in the UCON2 register, should also be set.  
Software should set the TX1E Bit when data is ready to be transmitted. It  
must be cleared by software when no more data needs to be transmitted.  
If this bit is '0' or TXD1F is set, the USB will respond with a NAK  
handshake to any Endpoint 1 or Endpoint 2 directed IN token.  
RESET clears this bit.  
5
TX1E  
R/W  
Force Resume.  
This bit forces a resume state (“K” on non-idle state) on the USB data  
www.BDTIC.com/ST  
4
FRESUM  
R/W  
lines to initiate a remote wake-up. Software should control the timing of  
the forced resume to be between 10ms and 15ms. Setting this bit will not  
cause the RESUMF Bit to set.  
TP1SIZ3 to  
TP1SIZ0  
3 to 0  
R/W  
The number of transmit data bytes. These bits are cleared by RESET.  
80/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 70. USB Control Register (UCON2: 0ECh)  
7
6
5
4
3
2
1
0
SOUT  
EP2E  
EP1E  
STALL2  
STALL1  
Table 71. Description of the UCON2 Bits  
Bit  
Symbol  
R/W  
Function  
7 to 5  
Reserved  
Status out is used to automatically respond to the OUT of a control  
READ transfer  
4
SOUT  
R/W  
3
2
1
0
EP2E  
EP1E  
R/W  
R/W  
R/W  
R/W  
Endpoint2 enable. RESET clears this bit  
Endpoint1 enable. RESET clears this bit  
Endpoint2 Force Stall Bit. RESET clears this bit  
Endpoint1 Force Stall Bit. RESET clears this bit  
STALL2  
STALL1  
Table 72. USB Endpoint0 Status Register (USTA: 0EDh)  
7
6
5
4
3
2
1
0
RSEQ  
SETUP  
IN  
OUT  
RP0SIZ3  
RP0SIZ2  
RP0SIZ1  
RP0SIZ0  
Table 73. Description of the USTA Bits  
Bit  
Symbol  
R/W  
Function  
Endpoint0 receive data packet PID. (0=DATA0, 1=DATA1)  
7
RSEQ  
R/W  
This bit will be compared with the type of data packet last received for  
Endpoint0  
www.BDTIC.com/ST  
SETUP Token Detect Bit. This bit is set when the received token packet  
is a SEPUP token, PID = b1101.  
6
5
SETUP  
R
R
R
R
IN Token Detect Bit.  
This bit is set when the received token packet is an IN token.  
IN  
OUT Token Detect Bit.  
This bit is set when the received token packet is an OUT token.  
4
OUT  
RP0SIZ3 to  
RP0SIZ0  
3 to 0  
The number of data bytes received in a DATA packet  
Table 74. USB Endpoint0 Data Receive Register (UDR0: 0EFh)  
7
6
5
4
3
2
1
0
UDR0.7  
UDR0.6  
UDR0.5  
UDR0.4  
UDR0.3  
UDR0.2  
UDR0.1  
UDR0.0  
Table 75. USB Endpoint0 Data Transmit Register (UDT0: 0E7h)  
7
6
5
4
3
2
1
0
UDT0.7  
UDT0.6  
UDT0.5  
UDT0.4  
UDT0.3  
UDT0.2  
UDT0.1  
UDT0.0  
Table 76. USB Endpoint1 Data Transmit Register (UDT1: 0E6h)  
7
6
5
4
3
2
1
0
UDT1.7  
UDT1.6  
UDT1.5  
UDT1.4  
UDT1.3  
UDT1.2  
UDT1.1  
UDT1.0  
81/163  
 
             
uPSD3212A, uPSD3212C, uPSD3212CV  
The USCL 8-bit Prescaler Register for USB is at  
E1h. The USCL should be loaded with a value that  
results in a clock rate of 6MHz for the USB using  
the following formula:  
Note: USB works ONLY with the MCU Clock fre-  
quencies of 12, 24, or 36MHz. The Prescaler val-  
ues for these frequencies are 0, 1, and 2.  
USB clock input =  
(f  
/ 2) / (Prescaler register value +1)  
OSC  
Where f  
is the MCU clock input frequency.  
OSC  
Table 77. USB SFR Memory Map  
Bit Register Name  
SFR Reg  
Addr Name  
Reset  
Value  
Comments  
7
6
5
4
3
2
1
0
8-bit  
E1 USCL  
00 Prescaler for  
USB logic  
USB Endpt1  
00  
E6 UDT1  
E7 UDT0  
UDT1.7 UDT1.6 UDT1.5 UDT1.4 UDT1.3 UDT1.2 UDT1.1 UDT1.0  
UDT0.7 UDT0.6 UDT0.5 UDT0.4 UDT0.3 UDT0.2 UDT0.1 UDT0.0  
Data Xmit  
USB Endpt0  
00  
Data Xmit  
USB  
E8 UISTA SUSPND  
RSTF  
TXD0F RXD0F RXD1F  
EOPF RESUMF 00 Interrupt  
Status  
USB  
E9 UIEN SUSPNDIE RSTE RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMIE 00 Interrupt  
Enable  
USB Endpt0  
Xmit Control  
EA UCON0 TSEQ0  
STALL0  
TX0E  
RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 00  
www.BDTIC.com/ST  
USB Endpt1  
Xmit Control  
EB UCON1 TSEQ1 EP12SEL  
IN  
FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 00  
SOUT EP2E EP1E STALL2 STALL1 00  
OUT RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 00  
USB Control  
Register  
EC UCON2  
ED USTA  
USB Endpt0  
Status  
RSEQ  
SETUP  
USB  
EE UADR  
EF UDR0  
USBEN  
UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0  
00 Address  
Register  
USB Endpt0  
Data Recv  
UDR0.7 UDR0.6 UDR0.5 UDR0.4 UDR0.3 UDR0.2 UDR0.1 UDR0.0  
00  
82/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Transceiver  
USB Physical Layer Characteristics. The fol-  
lowing section describes the uPSD321x Devices  
compliance to the Chapter 7 Electrical section of  
the USB Specification, Revision 1.1. The section  
contains all signaling, and physical layer specifica-  
tions necessary to describe a low speed USB  
function.  
tolerates a voltage on the signal pins of -0.5V to  
3.6V with respect to local ground reference without  
damage. The driver tolerates this voltage for  
10.0µs while the driver is active and driving, and  
tolerates this condition indefinitely when the driver  
is in its high impedance state.  
A low speed USB connection is made through an  
unshielded, untwisted wire cable a maximum of 3  
meters in length. The rise and fall time of the sig-  
nals on this cable are well controlled to reduce RFI  
emissions while limiting delays, signaling skews  
and distortions. The uPSD321x Devices driver  
reaches the specified static signal levels with  
smooth rise and fall times, resulting in segments  
between low speed devices and the ports to which  
they are connected.  
Low Speed Driver Characteristics. The  
uPSD321x Devices use a differential output driver  
to drive the Low Speed USB data signal onto the  
USB cable. The output swings between the differ-  
ential high and low state are well balanced to min-  
imize signal skew. The slew rate control on the  
driver minimizes the radiated noise and cross talk  
on the USB cable. The driver’s outputs support  
three-state operation to achieve bi-directional half  
duplex operation. The uPSD321x Devices driver  
Figure 40. Low Speed Driver Signal Waveforms  
One Bit  
Time  
1.5 Mb/s  
V
SE(max)  
Driver  
Signal pins  
pass output  
spec levels  
with minimal  
reflections and  
Signal Pins  
www.BDTIC.com/ST  
ringing  
VSE(min)  
VSS  
AI06629  
83/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 78. Transceiver DC Characteristics  
(1)  
Symb  
Parameter  
Static Output High  
Min  
2.8  
Max  
3.6  
Unit  
V
Test Conditions  
(2,3)  
V
OH  
15k± 5% to GND  
V
OL  
Static Output Low  
Notes 2, 3  
0.3  
V
|(D+) - (D-)|,  
V
Differential Input Sensitivity  
0.2  
V
DI  
V
Differential Input Common Mode  
Single Ended Receiver Threshold  
Transceiver Capacitance  
0.8  
0.8  
2.5  
2.0  
V
CM  
V
V
SE  
C
20  
pF  
µA  
kΩ  
kΩ  
IN  
I
Data Line (D+, D-) Leakage  
0V < (D+,D-) < 3.3  
–10  
7.35  
14.25  
10  
IO  
R
7.5k± 2% to V  
External Bus Pull-up Resistance, D-  
External Bus Pull-down Resistance  
7.65  
15.75  
PU  
CC  
R
15k± 5%  
PD  
Note: 1. V = 5V ± 10%; V = 0V; T = 0 to 70°C.  
CC  
SS  
A
2. Level guaranteed for range of V = 4.5V to 5.5V.  
CC  
3. With RPU, external idle resistor, 7.5κ±2%, D- to V  
.
CC  
Table 79. Transceiver AC Characteristics  
(1)  
Symb  
Parameter  
Min  
Max  
Unit  
Test Conditions  
tDRATE  
Low Speed Data Rate  
Ave. bit rate (1.5Mb/s ± 1.5%)  
1.4775  
1.5225  
Mbit/s  
To next transition,  
tDJR1  
Receiver Data Jitter Tolerance  
–75  
75  
ns  
ns  
(5)  
For paired transition,  
Diffewrentiawl Inpuwt Se.nsitivBity DTIC.com/ST45  
tDJR2  
–45  
(5)  
(5)  
tDEOP  
Differential to EOP Transition Skew  
–40  
165  
100  
ns  
ns  
ns  
µs  
(5,6)  
tEOPR1 EOP Width at Receiver  
tEOPR2 EOP Width at Receiver  
Rejects as EOP  
(5)  
675  
Accepts as EOP  
tEOPT  
tUDJ1  
Source EOP Width  
–1.25  
1.50  
To next transition,  
Differential Driver Jitter  
–95  
95  
ns  
ns  
To paired transition,  
tUDJ2  
Differential Driver Jitter  
–150  
150  
tR  
tF  
USB Data Transition Rise Time  
USB Data Transition Fall Time  
Rise/Fall Time Matching  
Notes 2, 3, 4  
Notes 2, 3, 4  
75  
75  
80  
1.3  
300  
300  
120  
2.0  
ns  
ns  
%
V
t
/ t  
F
tRFM  
VCRS  
R
Output Signal Crossover Volt age  
Note: 1. V = 5V ± 10%; V = 0V; T = 0 to 70°C.  
CC  
SS  
A
2. Level guaranteed for range of V = 4.5V to 5.5V.  
CC  
3. With RPU, external idle resistor, 7.5κ±2%, D- to V  
.
CC  
4. C of 50pF(75ns) to 350pF (300ns).  
L
5. Measured at crossover point of differential data signals.  
6. USB specification indicates 330ns.  
84/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Receiver Characteristics  
The uPSD321x Devices has a differential input re-  
ceiver which is able to accept the USB data signal.  
The receiver features an input sensitivity of at least  
200mV when both differential data inputs are in  
the range of at least 0.8V to 2.5V with respect to  
its local ground reference. This is the common  
mode range, as shown in Figure 41. The receiver  
tolerates static input voltages between -0.5V to  
3.8V with respect to its local ground reference  
without damage. In addition to the differential re-  
ceiver, there is a single-ended receiver for each of  
the two data lines. The single-ended receivers  
have a switching threshold between 0.8V and 2.0V  
(TTL inputs).  
Figure 41. Differential Input Sensitivity Over Entire Common Mode Range  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2  
Common Mode Input Voltage (volts)  
AI06630  
www.BDTIC.com/ST  
85/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
External USB Pull-Up Resistor  
The USB system specifies a pull-up resistor on the  
D- pin for low-speed peripherals. The USB  
Spec 1.1 describes a 1.5kpull-up resistor to a  
3.3V supply. An approved alternative method is a  
tive is defined for low-speed devices with an inte-  
grated cable. The chip is specified for the 7.5kΩ  
pull-up. This eliminates the need for an external  
3.3V regulator, or for a pin dedicated to providing  
a 3.3V output from the chip.  
7.5kpull-up to the USB V supply. This alterna-  
CC  
Figure 42. USB Data Signal Timing and Voltage Levels  
tR  
tF  
D+  
VOH  
90%  
90%  
VCR  
10%  
10%  
VOL  
D-  
AI06631  
Figure 43. Receiver Jitter Tolerance  
TPERIOD  
Differential  
Data Lines  
TJR2  
www.BDTIC.com/ST  
TJR  
TJR1  
Consecutive  
Transitions  
N*TPERIOD+TJR1  
Paired  
Transitions  
N*TPERIOD+TJR2  
AI06632  
86/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 44. Differential to EOP Transition Skew and EOP Width  
TPERIOD  
Crossover  
Point Extended  
Crossover  
Point  
Differential  
Data Lines  
Diff. Data to  
SE0 Skew  
N*TPERIOD+TDEOP  
Source EOP Width: TEOPT  
Receiver EOP Width  
T
EOPR1, TEOPR2  
AI06633  
Figure 45. Differential Data Jitter  
TPERIOD  
Crossover  
Points  
Differential  
Data Lines  
www.BDTIC.com/ST  
Consecutive  
Transitions  
N*TPERIOD+TxJR1  
Paired  
Transitions  
N*TPERIOD+TxJR2  
AI06634  
87/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
PSD MODULE  
The PSD Module provides configurable  
Program and Data memories to the 8032 CPU  
core (MCU). In addition, it has its own set of I/  
O ports and a PLD with 16 macrocells for  
general logic implementation.  
Decode PLD (DPLD) that decodes address for  
selection of memory blocks in the PSD  
Module.  
Configurable I/O ports (Port A,B,C and D) that  
can be used for the following functions:  
Ports A,B,C, and D are general purpose  
programmable I/O ports that have a port  
architecture which is different from the I/O  
ports in the MCU Module.  
The PSD Module communicates with the MCU  
Module through the internal address, data bus  
(A0-A15, D0-D7) and control signals (RD, WR,  
PSEN, ALE, RESET). The user defines the  
Decoding PLD in the PSDsoft Development  
Tool and can map the resources in the PSD  
Module to any program or data address  
space. Figure 46 shows the functional blocks  
in the PSD Module.  
MCU I/Os;  
PLD I/Os;  
Latched MCU address output; and  
Special function I/Os.  
Note: I/O ports may be configured as open drain  
outputs.  
Built-in JTAG compliant serial port allows full-  
chip, In-System Programmability (ISP). With  
it, you can program a blank device or  
reprogram a device in the factory or the field.  
Internal page register that can be used to  
expand the 8032 MCU Module address space  
by a factor of 256.  
Internal programmable Power Management  
Unit (PMU) that supports a low-power mode  
called Power-down Mode. The PMU can  
automatically detect a lack of the 8032 CPU  
core activity and put the PSD Module into  
Power-down Mode.  
Erase/WRITE cycles:  
Flash memory - 100,000 minimum  
PLD - 1,000 minimum  
Data Retention: 15 year minimum (for Main  
Flash memory, Boot, PLD and Configuration  
bits)  
Functional Overview  
512Kbit Flash memory. This is the main Flash  
memory. It is divided into 4 sectors (16KBytes  
each) that can be accessed with user-  
specified addresses.  
Secondary 128Kbit Flash boot memory. It is  
divided into 2 sectors (8KBytes each) that can  
be accessed with user-specified addresses.  
This secondary memory brings the ability to  
execute code and update the main Flash  
concurrently.  
www.BDTIC.com/ST  
16Kbit SRAM. The SRAM’s contents can be  
protected from a power failure by connecting  
an external battery.  
CPLD with 16 Output Micro Cells (OMCs) and  
up to 20 Input Micro Cells (IMCs). The CPLD  
may be used to efficiently implement a variety  
of logic functions for internal and external  
control. Examples include state machines,  
loadable shift registers, and loadable  
counters.  
88/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 46. PSD MODULE Block Diagram  
www.BDTIC.com/ST  
AI07431  
89/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
In-System Programming (ISP)  
Using the JTAG signals on Port C, the entire PSD  
MODULE device can be programmed or erased  
without the use of the MCU. The primary Flash  
memory can also be programmed in-system by  
the MCU executing the programming algorithms  
out of the secondary memory, or SRAM. The sec-  
ondary memory can be programmed the same  
way by executing out of the primary Flash memo-  
ry. The PLD or other PSD MODULE Configuration  
blocks can be programmed through the JTAG port  
or a device programmer. Table 80 indicates which  
programming methods can program different func-  
tional blocks of the PSD MODULE.  
Table 80. Methods of Programming Different Functional Blocks of the PSD MODULE  
Functional Block  
Primary Flash Memory  
JTAG Programming Device Programmer  
IAP  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
Secondary Flash Memory  
PLD Array (DPLD and CPLD)  
PSD MODULE Configuration  
No  
www.BDTIC.com/ST  
90/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
DEVELOPMENT SYSTEM  
The uPSD3200 is supported by PSDsoft, a Win-  
dows-based software development tool (Win-  
dows-95, Windows-98, Windows-NT). A PSD  
MODULE design is quickly and easily produced in  
a point and click environment. The designer does  
not need to enter Hardware Description Language  
(HDL) equations, unless desired, to define PSD  
MODULE pin functions and memory map informa-  
tion. The general design flow is shown in Figure  
47. PSDsoft is available from our web site (the ad-  
dress is given on the back page of this data sheet)  
or other distribution channels.  
PSDsoft directly supports a low cost device pro-  
grammer from ST: FlashLINK (JTAG). The pro-  
grammer may be purchased through your local  
distributor/representative. The uPSD3200 is also  
supported by third party device programmers. See  
our web site for the current list.  
Figure 47. PSDsoft Express Development Tool  
Choose µPSD  
Define µPSD Pin and  
Node Functions  
Point and click definition of  
PSD pin functions, internal nodes,  
and MCU system memory map  
www.BDTIC.com/ST  
Define General Purpose  
Logic in CPLD  
C Code Generation  
GENERATE C CODE  
SPECIFIC TO PSD  
FUNCTIONS  
Point and click definition of combin-  
atorial and registered logic in CPLD.  
Access HDL is available if needed  
Merge MCU Firmware with  
PSD Module Configuration  
USER'S CHOICE OF  
MCU FIRMWARE  
8032  
A composite object file is created  
containing MCU firmware and  
PSD configuration  
HEX OR S-RECORD  
FORMAT  
COMPILER/LINKER  
*.OBJ FILE  
PSD Programmer  
*.OBJ FILE  
AVAILABLE  
FOR 3rd PARTY  
PROGRAMMERS  
FlashLINK (JTAG)  
AI07432  
91/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET  
Table 81 shows the offset addresses to the PSD  
MODULE registers relative to the CSIOP base ad-  
dress. The CSIOP space is the 256 bytes of ad-  
dress that is allocated by the user to the internal  
PSD MODULE registers. Table 81 provides brief  
descriptions of the registers in CSIOP space. The  
following section gives a more detailed descrip-  
tion.  
Table 81. Register Address Offset  
1
Register Name  
Data In  
Port A Port B Port C Port D  
Description  
Other  
00  
02  
01  
03  
10  
11  
Reads Port pin as input, MCU I/O Input Mode  
Selects mode between MCU I/O or Address Out  
Control  
Stores data for output to Port pins, MCU I/O  
Output Mode  
Data Out  
Direction  
04  
06  
05  
07  
12  
14  
13  
15  
Configures Port pin as input or output  
Configures Port pins as either CMOS or Open  
Drain on some pins, while selecting high slew rate  
on other pins.  
Drive Select  
08  
09  
16  
17  
Input Macrocell  
Enable Out  
0A  
0C  
0B  
0D  
18  
1A  
Reads Input Macrocells  
Reads the status of the output enable to the I/O  
Port driver  
1B  
Output Macrocells  
AB  
READ – reads output of macrocells AB  
WRITE – loads macrocell flip-flops  
20  
20  
Output Macrocells  
BC  
READ – reads output of macrocells BC  
WRITE – loads macrocell flip-flops  
21  
22  
21  
Mask Macrocells AB 22  
Blocks writing to the Output Macrocells AB  
www.BDTIC.com/ST  
Blocks writing to the Output Macrocells BC  
Mask Macrocells BC  
23  
23  
Primary Flash  
Protection  
C0  
Read-only – Primary Flash Sector Protection  
Secondary Flash  
memory Protection  
Read-only – PSD MODULE Security and  
Secondary Flash memory Sector Protection  
C2  
PMMR0  
PMMR2  
Page  
B0  
B4  
E0  
Power Management Register 0  
Power Management Register 2  
Page Register  
Places PSD MODULE memory areas in Program  
and/or Data space on an individual basis.  
VM  
E2  
Note: 1. Other registers that are not part of the I/O ports.  
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uPSD3212A, uPSD3212C, uPSD3212CV  
Memory Block Select Signals  
The DPLD generates the Select signals for all the  
internal memory blocks (see PLDs, page 106).  
Each of the eight sectors of the primary Flash  
memory has a Select signal (FS0-FS3) which can  
contain up to three product terms. Each of the 2  
sectors of the secondary Flash memory has a Se-  
lect signal (CSBOOT0-CSBOOT1) which can con-  
tain up to three product terms. Having three  
product terms for each Select signal allows a given  
sector to be mapped in Program or Data space.  
Ready/Busy (PC3). This signal can be used to  
output the Ready/Busy status of the Flash memo-  
ry. The output on Ready/Busy (PC3) is a 0 (Busy)  
when Flash memory is being written to, or when  
Flash memory is being erased. The output is a 1  
(Ready) when no WRITE or Erase cycle is in  
progress.  
Memory Operation. The primary Flash memory  
and secondary Flash memory are addressed  
through the MCU Bus. The MCU can access these  
memories in one of two ways:  
PSD MODULE DETAILED OPERATION  
As shown in Figure 15., page 27, the PSD MOD-  
ULE consists of five major types of functional  
blocks:  
Memory Block  
PLD Blocks  
I/O Ports  
Power Management Unit (PMU)  
JTAG Interface  
The functions of each block are described in the  
following sections. Many of the blocks perform  
multiple functions, and are user configurable.  
MEMORY BLOCKS  
The PSD MODULE has the following memory  
blocks:  
Primary Flash memory  
Secondary Flash memory  
SRAM  
The MCU can execute a typical bus WRITE or  
READ operation.  
The Memory Select signals for these blocks origi-  
nate from the Decode PLD (DPLD) and are user-  
defined in PSDsoft Express.  
Primary Flash Memory and Secondary Flash  
memory Description  
The MCU can execute a specific Flash  
memory instruction that consists of several  
WRITE and READ operations. This involves  
writing specific data patterns to special  
addresses within the Flash memory to invoke  
an embedded algorithm. These instructions  
are summarized in Table 82.  
The primary Flash memory is divided into 4 sec-  
tors (16KBytes each). The secondary Flash mem-  
www.BDTIC.com/ST  
ory is divided into 2 sectors (8KBytes each). Each  
sector of either memory block can be separately  
protected from Program and Erase cycles.  
Flash memory may be erased on a sector-by-sec-  
tor basis. Flash sector erasure may be suspended  
while data is read from other sectors of the block  
and then resumed after reading.  
During a Program or Erase cycle in Flash memory,  
the status can be output on Ready/Busy (PC3).  
This pin is set up using PSDsoft Express Configu-  
ration.  
Typically, the MCU can read Flash memory using  
READ operations, just as it would read a ROM de-  
vice. However, Flash memory can only be altered  
using specific Erase and Program instructions. For  
example, the MCU cannot write a single byte di-  
rectly to Flash memory as it would write a byte to  
RAM. To program a byte into Flash memory, the  
MCU must execute a Program instruction, then  
test the status of the Program cycle. This status  
test is achieved by a READ operation or polling  
Ready/Busy (PC3).  
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uPSD3212A, uPSD3212C, uPSD3212CV  
Instructions  
An instruction consists of a sequence of specific  
operations. Each received byte is sequentially de-  
coded by the PSD MODULE and not executed as  
a standard WRITE operation. The instruction is ex-  
ecuted when the correct number of bytes are prop-  
erly received and the time between two  
consecutive bytes is shorter than the time-out pe-  
riod. Some instructions are structured to include  
READ operations after the initial WRITE opera-  
tions.  
The instruction must be followed exactly. Any in-  
valid combination of instruction bytes or time-out  
between two consecutive bytes while addressing  
Flash memory resets the device logic into READ  
Mode (Flash memory is read like a ROM device).  
These instructions are detailed in Table 82. For ef-  
ficient decoding of the instructions, the first two  
bytes of an instruction are the coded cycles and  
are followed by an instruction byte or confirmation  
byte. The coded cycles consist of writing the data  
AAh to address X555h during the first cycle and  
data 55h to address XAAAh during the second cy-  
cle. Address signals A15-A12 are Don’t Care dur-  
ing the instruction WRITE cycles. However, the  
appropriate  
Sector  
Select  
(FS0-FS3  
or  
CSBOOT0-CSBOOT1) must be selected.  
The primary and secondary Flash memories have  
the same instruction set. The Sector Select signals  
determine which Flash memory is to receive and  
execute the instruction. The primary Flash memo-  
ry is selected if any one of Sector Select (FS0-  
FS3) is High, and the secondary Flash memory is  
selected if any one of Sector Select (CSBOOT0-  
CSBOOT1) is High.  
The Flash memory supports the instructions sum-  
marized in Table 82., page 95:  
Flash memory:  
Erase memory by chip or sector  
Suspend or resume sector erase  
Program a Byte  
RESET to READ Mode  
Read Sector Protection Status  
www.BDTIC.com/ST  
94/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 82. Instructions  
FS0-FS3 or  
Instruction  
CSBOOT0-  
Cycle 1  
Cycle 2 Cycle 3  
Cycle 4  
Cycle 5 Cycle 6 Cycle 7  
CSBOOT1  
“Read”  
RD @ RA  
(5)  
1
1
1
1
1
1
1
1
READ  
READ Sector  
AAh@  
X555h  
55h@  
XAAAh  
90h@  
X555h  
Read status @  
XX02h  
(6,8,11)  
Protection  
Program a Flash  
AAh@  
X555h  
55h@  
XAAAh  
A0h@  
X555h  
PD@ PA  
(11)  
Byte  
(7)  
Flash Sector  
AAh@  
X555h  
55h@  
XAAAh  
80h@  
X555h  
55h@  
XAAAh  
30h@  
SA  
30h  
@
AAh@ X555h  
AAh@ X555h  
(7,11)  
Erase  
next SA  
Flash Bulk  
AAh@  
X555h  
55h@  
XAAAh  
80h@  
X555h  
55h@  
XAAAh  
10h@  
X555h  
(11)  
Erase  
Suspend Sector  
B0h@  
XXXXh  
(9)  
Erase  
Resume Sector  
30h@  
XXXXh  
(10)  
Erase  
F0h@  
XXXXh  
(6)  
RESET  
Note: 1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label  
2. All values are in hexadecimal:  
3. X = Don’t care. Addresses of the form XXXXh, in this table, must be even addresses  
4. RA = Address of the memory location to be read  
5. RD = Data READ from location RA during the READ cycle  
6. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR, CNTL0).  
7. PA is an even address for PSD in Word Programming Mode.  
8. PD = Data word to be programmed at location PA. Data is latched on the rising edge of WRITE Strobe (WR, CNTL0)  
www.BDTIC.com/ST  
9. SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1) of the sector to be  
erased, or verified, must be Active (High).  
10. Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1) signals are active High, and are defined in PSDsoft Express.  
11. Only address Bits A11-A0 are used in instruction decoding.  
12. No Unlock or instruction cycles are required when the device is in the READ Mode  
13. The RESET Instruction is required to return to the READ Mode after reading the Sector Protection Status, or if the Error Flag Bit  
(DQ5) goes High.  
14. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80µs.  
15. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and  
(A1,A0)=(1,0)  
16. The system may perform READ and Program cycles in non-erasing sectors, read the Sector Protection Status when in the Suspend  
Sector Erase Mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.  
17. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase Mode.  
18. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is  
intended. The MCU must retrieve, for example, the code from the secondary Flash memory when reading the Sector Protection  
Status of the primary Flash memory.  
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uPSD3212A, uPSD3212C, uPSD3212CV  
Power-down Instruction and Power-up Mode  
Power-up Mode. The PSD MODULE internal  
logic is reset upon Power-up to the READ Mode.  
Sector Select (FS0-FS3 and CSBOOT0-  
CSBOOT1) must be held Low, and WRITE Strobe  
(WR, CNTL0) High, during Power-up for maximum  
security of the data contents and to remove the  
possibility of a byte being written on the first edge  
of WRITE Strobe (WR, CNTL0). Any WRITE cycle  
ter definitions.  
Reading the Erase/Program Status Bits. The  
Flash memory provides several status bits to be  
used by the MCU to confirm the completion of an  
Erase or Program cycle of Flash memory. These  
status bits minimize the time that the MCU spends  
performing these tasks and are defined in Table  
83., page 97. The status bits can be read as many  
times as needed.  
initiation is locked when V is below V  
.
CC  
LKO  
READ  
Under typical conditions, the MCU may read the  
primary Flash memory or the secondary Flash  
memory using READ operations just as it would a  
ROM or RAM device. Alternately, the MCU may  
use READ operations to obtain status information  
about a Program or Erase cycle that is currently in  
progress. Lastly, the MCU may use instructions to  
read special data from these memory blocks. The  
following sections describe these READ functions.  
READ Memory Contents. Primary Flash memo-  
ry and secondary Flash memory are placed in the  
READ Mode after Power-up, chip reset, or a  
Reset Flash instruction (see Table 82., page 95).  
The MCU can read the memory contents of the pri-  
mary Flash memory or the secondary Flash mem-  
ory by using READ operations any time the READ  
operation is not part of an instruction.  
For Flash memory, the MCU can perform a READ  
operation to obtain these status bits while an  
Erase or Program instruction is being executed by  
the embedded algorithm. See Programming Flash  
Memory, page 98, for details.  
Data Polling Flag (DQ7). When erasing or pro-  
gramming in Flash memory, the Data Polling Flag  
Bit (DQ7) outputs the complement of the bit being  
entered for programming/writing on the DQ7 Bit.  
Once the Program instruction or the WRITE oper-  
ation is completed, the true logic value is read on  
the Data Polling Flag Bit (DQ7) (in a READ opera-  
tion).  
Data Polling is effective after the fourth WRITE  
pulse (for a Program instruction) or after the  
sixth WRITE pulse (for an Erase instruction). It  
must be performed at the address being  
programmed or at an address within the Flash  
memory sector being erased.  
READ Memory Sector Protection Status. The  
primary Flash memory Sector Protection Status is  
read with an instwructiown cowmpo.sedBof 4 oDperaTtionIs: C.com/ST  
During an Erase cycle, the Data Polling Flag  
3 specific WRITE operations and a READ opera-  
tion (see Table 82). During the READ operation,  
address Bits A6, A1, and A0 must be '0,' '1,' and  
'0,' respectively, while Sector Select (FS0-FS3 or  
CSBOOT0-CSBOOT1) designates the Flash  
memory sector whose protection has to be veri-  
fied. The READ operation produces 01h if the  
Flash memory sector is protected, or 00h if the  
sector is not protected.  
Bit (DQ7) outputs a '0.' After completion of the  
cycle, the Data Polling Flag Bit (DQ7) outputs  
the last bit programmed (it is a '1' after  
erasing).  
If the byte to be programmed is in a protected  
Flash memory sector, the instruction is  
ignored.  
If all the Flash memory sectors to be erased  
are protected, the Data Polling Flag Bit (DQ7)  
is reset to '0' for about 100µs, and then returns  
to the previous addressed byte. No erasure is  
performed.  
The sector protection status for all NVM blocks  
(primary Flash memory or secondary Flash mem-  
ory) can also be read by the MCU accessing the  
Flash Protection registers in PSD I/O space. See  
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uPSD3212A, uPSD3212C, uPSD3212CV  
Toggle Flag (DQ6). The Flash memory offers an-  
other way for determining when the Program cycle  
is completed. During the internal WRITE operation  
and when either the FS0-FS3 or CSBOOT0-  
CSBOOT1 is true, the Toggle Flag Bit (DQ6) tog-  
gles from 0 to 1 and 1 to 0 on subsequent attempts  
to read any byte of the memory.  
When the internal cycle is complete, the toggling  
stops and the data READ on the Data Bus D0-D7  
is the addressed memory byte. The device is now  
accessible for a new READ or WRITE operation.  
The cycle is finished when two successive Reads  
yield the same output data.  
bit is set to '1' when there is a failure during Flash  
memory Byte Program, Sector Erase, or Bulk  
Erase cycle.  
In the case of Flash memory programming, the Er-  
ror Flag Bit (DQ5) indicates the attempt to program  
a Flash memory bit from the programmed state,  
'0,' to the erased state, '1,' which is not valid. The  
Error Flag Bit (DQ5) may also indicate a Time-out  
condition while attempting to program a byte.  
In case of an error in a Flash memory Sector Erase  
or Byte Program cycle, the Flash memory sector in  
which the error occurred or to which the pro-  
grammed byte belongs must no longer be used.  
Other Flash memory sectors may still be used.  
The Error Flag Bit (DQ5) is reset after a Reset  
Flash instruction.  
Erase Time-out Flag (DQ3). The Erase Time-  
out Flag Bit (DQ3) reflects the time-out period al-  
lowed between two consecutive Sector Erase in-  
structions. The Erase Time-out Flag Bit (DQ3) is  
reset to 0 after a Sector Erase cycle for a time pe-  
riod of 100µs + 20% unless an additional Sector  
Erase instruction is decoded. After this time peri-  
od, or when the additional Sector Erase instruction  
is decoded, the Erase Time-out Flag Bit (DQ3) is  
set to '1.'  
The Toggle Flag Bit (DQ6) is effective after the  
fourth WRITE pulse (for a Program instruction)  
or after the sixth WRITE pulse (for an Erase  
instruction).  
If the byte to be programmed belongs to a  
protected Flash memory sector, the  
instruction is ignored.  
If all the Flash memory sectors selected for  
erasure are protected, the Toggle Flag Bit  
(DQ6) toggles to '0' for about 100µs and then  
returns to the previous addressed byte.  
Error Flag (DQ5). During a normal Program or  
Erase cycle, the Error Flag Bit (DQ5) is to 0. This  
Table 83. Status Bit  
FS0-FS3/CSBOOT0-  
Functional Block  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
www.BDTIC.com/ST  
DQ2  
DQ1  
DQ0  
CSBOOT1  
Erase  
Time-  
out  
Data  
Polling Flag  
Toggle Error  
V
Flash Memory  
X
X
X
X
IH  
Flag  
Note: 1. X = Not guaranteed value, can be read either '1' or '0.'  
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.  
3. FS0-FS3 and CSBOOT0-CSBOOT1 are active High.  
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uPSD3212A, uPSD3212C, uPSD3212CV  
Programming Flash Memory  
Flash memory must be erased prior to being pro-  
grammed. A byte of Flash memory is erased to all  
'1s' (FFh), and is programmed by setting selected  
bits to '0.' The MCU may erase Flash memory all  
at once or by-sector, but not byte-by-byte. Howev-  
er, the MCU may program Flash memory byte-by-  
byte.  
The primary and secondary Flash memories re-  
quire the MCU to send an instruction to program a  
byte or to erase sectors (see Table 82).  
Once the MCU issues a Flash memory Program or  
Erase instruction, it must check for the status bits  
for completion. The embedded algorithms that are  
invoked support several means to provide status  
to the MCU. Status may be checked using any of  
three methods: Data Polling, Data Toggle, or  
Ready/Busy (PC3).  
byte that was written to the Flash memory with the  
byte that was intended to be written.  
When using the Data Polling method during an  
Erase cycle, Figure 48 still applies. However, the  
Data Polling Flag Bit (DQ7) is '0' until the Erase cy-  
cle is complete. A '1' on the Error Flag Bit (DQ5) in-  
dicates a time-out condition on the Erase cycle; a  
'0' indicates no error. The MCU can read any loca-  
tion within the sector being erased to get the Data  
Polling Flag Bit (DQ7) and the Error Flag Bit  
(DQ5).  
PSDsoft Express generates ANSI C code func-  
tions which implement these Data Polling algo-  
rithms.  
Figure 48. Data Polling Flowchart  
Data Polling. Polling on the Data Polling Flag Bit  
(DQ7) is a method of checking whether a Program  
or Erase cycle is in progress or has completed.  
Figure 48 shows the Data Polling algorithm.  
When the MCU issues a Program instruction, the  
embedded algorithm begins. The MCU then reads  
the location of the byte to be programmed in Flash  
memory to check status. The Data Polling Flag Bit  
(DQ7) of this location becomes the complement of  
b7 of the original data byte to be programmed. The  
MCU continues to poll this location, comparing the  
Data Polling Flag Bit (DQ7) and monitoring the Er-  
START  
READ DQ5 & DQ7  
at VALID ADDRESS  
DQ7  
=
DATA  
YES  
NO  
NO  
www.BDTIC.com/ST  
ror Flag Bit (DQ5). When the Data Polling Flag Bit  
DQ5  
= 1  
(DQ7) matches b7 of the original data, and the Er-  
ror Flag Bit (DQ5) remains '0,' the embedded algo-  
rithm is complete. If the Error Flag Bit (DQ5) is '1,'  
the MCU should test the Data Polling Flag Bit  
(DQ7) again since the Data Polling Flag Bit (DQ7)  
may have changed simultaneously with the Error  
Flag Bit (DQ5) (see Figure 48).  
YES  
READ DQ7  
DQ7  
=
DATA  
YES  
The Error Flag Bit (DQ5) is set if either an internal  
time-out occurred while the embedded algorithm  
attempted to program the byte or if the MCU at-  
tempted to program a '1' to a bit that was not  
erased (not erased is logic '0').  
NO  
FAIL  
PASS  
It is suggested (as with all Flash memories) to read  
the location again after the embedded program-  
ming algorithm has completed, to compare the  
AI01369B  
98/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Data Toggle. Checking the Toggle Flag Bit  
(DQ6) is a method of determining whether a Pro-  
gram or Erase cycle is in progress or has complet-  
ed. Figure 49 shows the Data Toggle algorithm.  
indicates no error. The MCU can read any location  
within the sector being erased to get the Toggle  
Flag Bit (DQ6) and the Error Flag Bit (DQ5).  
PSDsoft Express generates ANSI C code func-  
tions which implement these Data Toggling algo-  
rithms.  
When the MCU issues a Program instruction, the  
embedded algorithm begins. The MCU then reads  
the location of the byte to be programmed in Flash  
memory to check status. The Toggle Flag Bit  
(DQ6) of this location toggles each time the MCU  
reads this location until the embedded algorithm is  
complete. The MCU continues to read this loca-  
tion, checking the Toggle Flag Bit (DQ6) and mon-  
itoring the Error Flag Bit (DQ5). When the Toggle  
Flag Bit (DQ6) stops toggling (two consecutive  
reads yield the same value), and the Error Flag Bit  
(DQ5) remains '0,' the embedded algorithm is  
complete. If the Error Flag Bit (DQ5) is '1,' the  
MCU should test the Toggle Flag Bit (DQ6) again,  
since the Toggle Flag Bit (DQ6) may have  
changed simultaneously with the Error Flag Bit  
(DQ5) (see Figure 49).  
Figure 49. Data Toggle Flowchart  
START  
READ  
DQ5 & DQ6  
DQ6  
NO  
=
TOGGLE  
YES  
The Error Flag Bit(DQ5) is set if either an internal  
time-out occurred while the embedded algorithm  
attempted to program the byte, or if the MCU at-  
tempted to program a '1' to a bit that was not  
erased (not erased is logic '0').  
NO  
DQ5  
= 1  
YES  
READ DQ6  
It is suggested (as with all Flash memories) to read  
the location again after the embedded program-  
ming algorithm has completed, to compare the  
byte that was written to Flash memory with the  
byte that was intended to be written.  
DQ6  
=
NO  
TOGGLE  
www.BDTIC.com/ST  
YES  
When using the Data Toggle method after an  
FAIL  
PASS  
Erase cycle, Figure 49 still applies. the Toggle  
Flag Bit (DQ6) toggles until the Erase cycle is  
complete. A '1' on the Error Flag Bit (DQ5) indi-  
cates a time-out condition on the Erase cycle; a '0'  
AI01370B  
99/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Erasing Flash Memory  
Flash Bulk Erase. The Flash Bulk Erase instruc-  
tion uses six WRITE operations followed by a  
READ operation of the status register, as de-  
scribed in Table 82. If any byte of the Bulk Erase  
instruction is wrong, the Bulk Erase instruction  
aborts and the device is reset to the READ Flash  
memory status.  
During a Bulk Erase, the memory status may be  
checked by reading the Error Flag Bit (DQ5), the  
Toggle Flag Bit (DQ6), and the Data Polling Flag  
Bit (DQ7), as detailed in Programming Flash  
Memory, page 98. The Error Flag Bit (DQ5) re-  
turns a '1' if there has been an Erase Failure (max-  
imum number of Erase cycles have been  
executed).  
It is not necessary to program the memory with  
00h because the PSD MODULE automatically  
does this before erasing to 0FFh.  
During execution of the Bulk Erase instruction, the  
Flash memory does not accept any instructions.  
Flash Sector Erase. The Sector Erase instruc-  
tion uses six WRITE operations, as described in  
Table 82., page 95. Additional Flash Sector Erase  
codes and Flash memory sector addresses can be  
written subsequently to erase other Flash memory  
sectors in parallel, without further coded cycles, if  
the additional bytes are transmitted in a shorter  
time than the time-out period of about 100µs. The  
input of a new Sector Erase code restarts the time-  
During execution of the Erase cycle, the Flash  
memory accepts only RESET and Suspend Sec-  
tor Erase instructions. Erasure of one Flash mem-  
ory sector may be suspended, in order to read  
data from another Flash memory sector, and then  
resumed.  
Suspend Sector Erase. When a Sector Erase  
cycle is in progress, the Suspend Sector Erase in-  
struction can be used to suspend the cycle by writ-  
ing 0B0h to any address when an appropriate  
Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1)  
is High. (See Table 82., page 95). This allows  
reading of data from another Flash memory sector  
after the Erase cycle has been suspended. Sus-  
pend Sector Erase is accepted only during an  
Erase cycle and defaults to READ Mode. A Sus-  
pend Sector Erase instruction executed during an  
Erase time-out period, in addition to suspending  
the Erase cycle, terminates the time out period.  
The Toggle Flag Bit (DQ6) stops toggling when the  
internal logic is suspended. The status of this bit  
must be monitored at an address within the Flash  
memory sector being erased. The Toggle Flag Bit  
(DQ6) stops toggling between 0.1µs and 15µs af-  
ter the Suspend Sector Erase instruction has been  
executed. The Flash memory is then automatically  
set to READ Mode.  
If an Suspend Sector Erase instruction was exe-  
cuted, the following rules apply:  
www.BDTIC.com/ST  
out period.  
Attempting to read from a Flash memory  
sector that was being erased outputs invalid  
data.  
The status of the internal timer can be monitored  
through the level of the Erase Time-out Flag Bit  
(DQ3). If the Erase Time-out Flag Bit (DQ3) is '0,'  
the Sector Erase instruction has been received  
and the time-out period is counting. If the Erase  
Time-out Flag Bit (DQ3) is '1,' the time-out period  
has expired and the embedded algorithm is busy  
erasing the Flash memory sector(s). Before and  
during Erase time-out, any instruction other than  
Suspend Sector Erase and Resume Sector Erase  
instructions abort the cycle that is currently in  
progress, and reset the device to READ Mode.  
Reading from a Flash sector that was not  
being erased is valid.  
The Flash memory cannot be programmed,  
and only responds to Resume Sector Erase  
and Reset Flash instructions (READ is an  
operation and is allowed).  
If a Reset Flash instruction is received, data in  
the Flash memory sector that was being  
erased is invalid.  
Resume Sector Erase. If  
a
Suspend Sector  
During a Sector Erase, the memory status may be  
checked by reading the Error Flag Bit (DQ5), the  
Toggle Flag Bit (DQ6), and the Data Polling Flag  
Bit (DQ7), as detailed in Programming Flash  
Erase instruction was previously executed, the  
erase cycle may be resumed with this instruction.  
The Resume Sector Erase instruction consists of  
writing 030h to any address while an appropriate  
Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1)  
is High. (See Table 82., page 95.)  
100/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Specific Features  
Flash Memory Sector Protect. Each  
primary  
Reset Flash. The Reset Flash instruction con-  
sists of one WRITE cycle (see Table  
82., page 95). It can also be optionally preceded  
by the standard two WRITE decoding cycles (writ-  
ing AAh to 555h and 55h to AAAh). It must be ex-  
ecuted after:  
and secondary Flash memory sector can be sepa-  
rately protected against Program and Erase cy-  
cles. Sector Protection provides additional data  
security because it disables all Program or Erase  
cycles. This mode can be activated through the  
JTAG Port or a Device Programmer.  
Sector protection can be selected for each sector  
using the PSDsoft Express Configuration pro-  
gram. This automatically protects selected sectors  
when the device is programmed through the JTAG  
Port or a Device Programmer. Flash memory sec-  
tors can be unprotected to allow updating of their  
contents using the JTAG Port or a Device Pro-  
grammer. The MCU can read (but cannot change)  
the sector protection bits.  
Any attempt to program or erase a protected Flash  
memory sector is ignored by the device. The Verify  
operation results in a READ of the protected data.  
This allows a guarantee of the retention of the Pro-  
tection status.  
The sector protection status can be read by the  
MCU through the Flash memory protection regis-  
ters (in the CSIOP block). See Tables 84 and 85.  
Reading the Flash Protection Status or Flash  
ID  
An Error condition has occurred (and the  
device has set the Error Flag Bit (DQ5) to '1'  
during a Flash memory Program or Erase  
cycle.  
The Reset Flash instruction puts the Flash memo-  
ry back into normal READ Mode. If an Error condi-  
tion has occurred (and the device has set the Error  
Flag Bit (DQ5) to '1' the Flash memory is put back  
into normal READ Mode within a few milliseconds  
of the Reset Flash instruction having been issued.  
The Reset Flash instruction is ignored when it is is-  
sued during a Program or Bulk Erase cycle of the  
Flash memory. The Reset Flash instruction aborts  
any on-going Sector Erase cycle, and returns the  
Flash memory to the normal READ Mode within a  
few milliseconds.  
Table 84. Sector Protection/Security Bit Definition – Flash Protection Register  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
not used  
not used  
not used  
not used  
Sec3_Prot  
Sec2_Prot  
Sec1_Prot  
www.BDTIC.com/ST  
Sec0_Prot  
Note: Bit Definitions:  
Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write-protected.  
Sec<i>_Prot 0 = Primary Flash memory or secondary Flash memory Sector <i> is not write-protected.  
Table 85. Sector Protection/Security Bit Definition – Secondary Flash Protection Register  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Security_Bit not used  
Note: Bit Definitions:  
not used  
not used  
not used  
not used  
Sec1_Prot  
Sec0_Prot  
Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write-protected.  
Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write-protected.  
Security_Bit 0 = Security Bit in device has not been set; 1 = Security Bit in device has been set.  
101/163  
 
       
uPSD3212A, uPSD3212C, uPSD3212CV  
SRAM  
6. SRAM, I/O, and Peripheral I/O spaces may  
overlap any other memory sector. Priority is  
given to the SRAM, I/O, or Peripheral I/O.  
Example. FS0 is valid when the address is in the  
range of 8000h to BFFFh, CSBOOT0 is valid from  
8000h to 9FFFh, and RS0 is valid from 8000h to  
87FFh. Any address in the range of RS0 always  
accesses the SRAM. Any address in the range of  
CSBOOT0 greater than 87FFh (and less than  
9FFFh) automatically addresses secondary Flash  
memory segment 0. Any address greater than  
9FFFh accesses the primary Flash memory seg-  
ment 0. You can see that half of the primary Flash  
memory segment 0 and one-fourth of secondary  
Flash memory segment 0 cannot be accessed in  
this example.  
tery. Battery-on Indicator (V  
with the supply voltage falls below the battery volt-  
, PC4) is High  
Note: An equation that defined FS1 to anywhere  
in the range of 8000h to BFFFh would not be valid.  
BATON  
age and the battery on Voltage Standby (V  
PC2) is supplying power to the internal SRAM.  
SRAM Select (RS0), Voltage Standby (V  
,
STBY  
Figure 50 shows the priority levels for all memory  
components. Any component on a higher level can  
overlap and has priority over any component on a  
lower level. Components on the same level must  
not overlap. Level one has the highest priority and  
level 3 has the lowest.  
,
STBY  
PC2) and Battery-on Indicator (V  
, PC4) are  
BATON  
all configured using PSDsoft Express Configura-  
tion.  
Sector Select and SRAM Select  
Figure 50. Priority Level of Memory and I/O  
Components in the PSD MODULE  
Sector Select (FS0-FS3, CSBOOT0-CSBOOT1)  
and SRAM Select (RS0) are all outputs of the  
DPLD. They are setup by writing equations for  
them in PSDsoft Express. The following rules ap-  
www.BDTIC.com/ST  
ply to the equations for these signals:  
Highest Priority  
1. Primary Flash memory and secondary Flash  
memory Sector Select signals must not be  
larger than the physical sector size.  
Level 1  
SRAM, I/O, or  
Peripheral I/O  
2. Any primary Flash memory sector must not be  
mapped in the same memory space as  
another Flash memory sector.  
3. A secondary Flash memory sector must notbe  
mapped in the same memory space as  
Level 2  
Secondary  
Non-Volatile Memory  
Level 3  
Primary Flash Memory  
another secondary Flash memory sector.  
4. SRAM, I/O, and Peripheral I/O spaces must  
not overlap.  
Lowest Priority  
AI02867D  
5. A secondary Flash memory sector may  
overlap a primary Flash memory sector. In  
case of overlap, priority is given to the  
secondary Flash memory sector.  
102/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Memory Select Configuration in Program and  
Data Spaces. The MCU Core has separate ad-  
dress spaces for Program memory and Data  
memory. Any of the memories within the PSD  
MODULE can reside in either space or both spac-  
es. This is controlled through manipulation of the  
VM Register that resides in the CSIOP space.  
The VM Register is set using PSDsoft Express to  
have an initial value. It can subsequently be  
changed by the MCU so that memory mapping  
can be changed on-the-fly.  
For example, you may wish to have SRAM and pri-  
mary Flash memory in the Data space at Boot-up,  
and secondary Flash memory in the Program  
space at Boot-up, and later swap the primary and  
secondary Flash memories. This is easily done  
with the VM Register by using PSDsoft Express  
Configuration to configure it for Boot-up and hav-  
ing the MCU change it when desired. Table 86 de-  
scribes the VM Register.  
Table 86. VM Register  
Bit 4  
Bit 2  
Primary  
FL_Code  
Bit 7  
Bit 3  
Secondary Data  
Bit 1  
Bit 0  
Bit 6  
Bit 5  
Primary  
PIO_EN  
Secondary Code SRAM_Code  
FL_Data  
0 = RD  
can’t  
0 = PSEN  
can’t  
access Secondary access  
0 = PSEN  
0 = PSEN can’t  
can’t  
0 = RD can’t  
0 = disable  
PIO Mode  
not used not used access  
access Secondary  
access  
Flash  
memory  
Flash memory  
Flash  
memory  
Flash memory  
SRAM  
1 = RD  
1 = PSEN  
access  
Flash  
1 = RD access  
Secondary Flash  
memory  
1 = PSEN access 1 = PSEN  
1= enable  
PIO Mode  
access  
not used not used  
Flash  
Secondary Flash  
memory  
access  
SRAM  
memory  
memory  
www.BDTIC.com/ST  
103/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Separate Space Mode. Program space is sepa-  
rated from Data space. For example, Program Se-  
lect Enable (PSEN) is used to access the program  
code from the primary Flash memory, while READ  
Strobe (RD) is used to access data from the sec-  
ondary Flash memory, SRAM and I/O Port blocks.  
This configuration requires the VM Register to be  
set to 0Ch (see Figure 51).  
Combined Space Modes. The Program and  
Data spaces are combined into one memory  
space that allows the primary Flash memory, sec-  
ondary Flash memory, and SRAM to be accessed  
by either Program Select Enable (PSEN) or READ  
Strobe (RD). For example, to configure the prima-  
ry Flash memory in Combined space, Bits b2 and  
b4 of the VM Register are set to '1' (see Figure 52).  
Figure 51. Separate Space Mode  
Primary  
Flash  
Secondary  
Flash  
SRAM  
DPLD  
RS0  
Memory  
Memory  
CSBOOT0-1  
FS0-FS3  
CS  
CS  
OE  
CS  
OE  
OE  
PSEN  
RD  
AI07433  
Figure 52. Combined Space Mode  
www.BDTIC.com/ST  
Secondary  
Flash  
Primary  
Flash  
Memory  
SRAM  
DPLD  
RS0  
Memory  
RD  
CSBOOT0-1  
FS0-FS3  
CS  
CS  
CS  
OE  
OE  
OE  
VM REG BIT 3  
VM REG BIT 4  
PSEN  
VM REG BIT 1  
RD  
VM REG BIT 2  
VM REG BIT 0  
AI07434  
104/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Page Register  
The 8-bit Page Register increases the addressing  
capability of the MCU Core by a factor of up to 256.  
The contents of the register can also be read by  
the MCU. The outputs of the Page Register  
(PGR0-PGR7) are inputs to the DPLD decoder  
and can be included in the Sector Select (FS0-  
FS3, CSBOOT0-CSBOOT1), and SRAM Select  
(RS0) equations.  
If memory paging is not needed, or if not all 8 page  
register bits are needed for memory paging, then  
these bits may be used in the CPLD for general  
logic.  
Figure 53 shows the Page Register. The eight flip-  
flops in the register are connected to the internal  
data bus D0-D7. The MCU can write to or read  
from the Page Register. The Page Register can be  
accessed at address location CSIOP + E0h.  
Figure 53. Page Register  
RESET  
PGR0  
INTERNAL PSD MODULE  
SELECTS  
AND LOGIC  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Q0  
PGR1  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
PGR2  
D0 - D7  
DPLD  
AND  
CPLD  
PGR3  
PGR4  
PGR5  
PGR6  
PGR7  
R/W  
PAGE  
REGISTER  
PLD  
AI05799  
www.BDTIC.com/ST  
105/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
PLDS  
The PLDs bring programmable logic functionality  
to the uPSD. After specifying the logic for the  
PLDs in PSDsoft Express, the logic is pro-  
grammed into the device and available upon Pow-  
er-up.  
The PSD MODULE contains two PLDs: the De-  
code PLD (DPLD), and the Complex PLD (CPLD).  
The PLDs are briefly discussed in the next few  
paragraphs, and in more detail in Decode PLD  
and  
the configuration of the PLDs.  
The DPLD performs address decoding for Select  
signals for PSD MODULE components, such as  
memory, registers, and I/O ports.  
Table 87. DPLD and CPLD Inputs  
Number  
Input Source  
Input Name  
of  
Signals  
The CPLD can be used for logic functions, such as  
loadable counters and shift registers, state ma-  
chines, and encoding and decoding logic. These  
logic functions can be constructed using the Out-  
put Macrocells (OMC), Input Macrocells (IMC),  
and the AND Array. The CPLD can also be used  
to generate External Chip Select (ECS1-ECS2)  
signals.  
MCU Address Bus  
A15-A0  
16  
4
PSEN, RD, WR,  
ALE  
MCU Control Signals  
RESET  
RST  
PDN  
1
1
Power-down  
Port A Input  
The AND Array is used to form product terms.  
These product terms are specified using PSDsoft.  
The PLD input signals consist of internal MCU sig-  
nals and external inputs from the I/O ports. The in-  
put signals are shown in Table 87.  
PA7-PA0  
8
8
4
1
Macrocells  
Port B Input  
Macrocells  
PB7-PB0  
Port C Input  
Macrocells  
The Turbo Bit in PSD MODULE  
PC7, PC4-PC2  
The PLDs can minimize power consumption by  
switching off when inputs remain unchanged for  
an extended time of about 70ns. Resetting the  
Turbo Bit to '0' (Bit 3 of PMMR0) automatically  
places the PLDs into standby if no inputs are  
Port D Inputs  
Page Register  
Macrocell AB  
PD2-PD1  
2
8
PGR7-PGR0  
MCELLAB.FB7-  
www.BDTIC.com/ST  
8
changing. Turning the Turbo Mode off increases  
Feedback  
FB0  
propagation delays while reducing power con-  
sumption.  
Macrocell BC  
Feedback  
MCELLBC.FB7-  
FB0  
8
to set the Turbo Bit.  
Additionally, five bits are available in PMMR2 to  
block MCU control signals from entering the PLDs.  
This reduces power consumption and can be used  
only when these MCU control signals are not used  
in PLD logic equations.  
Flash memory  
Program Status Bit  
Ready/Busy  
1
Note: 1. These inputs are not available in the 52-pin package.  
Each of the two PLDs has unique characteristics  
suited for its applications. They are described in  
the following sections.  
106/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 54. PLD Diagram  
8
PAGE  
DATA  
REGISTER  
BUS  
DECODE PLD  
4
73  
PRIMARY FLASH MEMORY SELECTS  
2
1
1
2
SECONDARY NON-VOLATILE MEMORY SELECTS  
SRAM SELECT  
CSIOP SELECT  
PERIPHERAL SELECTS  
OUTPUT MACROCELL FEEDBACK  
CPLD  
DIRECT MACROCELL ACCESS FROM MCU DATA BUS  
MCELLAB  
16  
16 OUTPUT  
MACROCELL  
1
TO PORT A OR B  
8
MACROCELL  
ALLOC.  
PT  
ALLOC.  
73  
MCELLBC  
TO PORT B OR C  
8
2
20 INPUT MACROCELL  
(PORT A,B,C)  
EXTERNAL CHIP SELECTS  
TO PORT D  
DIRECT MACROCELL INPUT TO MCU DATA BUS  
www.BDTIC.com/ST  
INPUT MACROCELL & INPUT PORTS  
20  
2
PORT D INPUTS  
AI07435  
Note: 1. Ports A is not available in the 52-pin package  
107/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Decode PLD (DPLD)  
The DPLD, shown in Figure 55, is used for decod-  
ing the address for PSD MODULE and external  
components. The DPLD can be used to generate  
the following decode signals:  
2 Sector Select (CSBOOT0-CSBOOT1)  
signals for the secondary Flash memory (three  
product terms each)  
1 internal SRAM Select (RS0) signal (two  
product terms)  
1 internal CSIOP Select signal (selects the  
PSD MODULE registers)  
2 internal Peripheral Select signals  
(Peripheral I/O Mode).  
4 Sector Select (FS0-FS3) signals for the  
primary Flash memory (three product terms  
each)  
Figure 55. DPLD Logic Array  
CSBOOT 0  
CSBOOT 1  
3
3
(INPUTS)  
3
3
3
3
FS0  
1
I/O PORTS (PORT A,B,C)  
(20)  
4 PRIMARY FLASH  
MEMORY SECTOR  
SELECTS  
FS1  
FS2  
(8)  
MCELLAB.FB [7:0] (FEEDBACKS)  
MCELLBC.FB [7:0] (FEEDBACKS)  
(8)  
(8)  
FS3  
PGR0 -PGR7  
2
(16)  
www.BDTIC.com/ST  
[
]
A 15:0  
(2)  
[
]
PD 2:1  
PDN (APD OUTPUT)  
(1)  
2
(4)  
(1)  
(1)  
PSEN, RD, WR, ALE  
2
RESET  
RS0  
2
1
SRAM SELECT  
RD_BSY  
CSIOP  
I/O DECODER  
SELECT  
PSEL0  
PSEL1  
1
1
PERIPHERAL I/O  
MODE SELECT  
AI07436  
Note: 1. Port A inputs are not available in the 52-pin package  
2. Inputs from the MCU module  
108/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Complex PLD (CPLD)  
The CPLD can be used to implement system logic  
functions, such as loadable counters and shift reg-  
isters, system mailboxes, handshaking protocols,  
state machines, and random logic. The CPLD can  
also be used to generate External Chip Select  
(ECS1-ECS2), routed to Port D.  
Although External Chip Select (ECS1-ECS2) can  
be produced by any Output Macrocell (OMC),  
these External Chip Select (ECS1-ECS2) on Port  
D do not consume any Output Macrocells (OMC).  
AND Array capable of generating up to 137  
product terms  
Four I/O Ports.  
Each of the blocks are described in the sections  
that follow.  
The Input Macrocells (IMC) and Output Macrocells  
(OMC) are connected to the PSD MODULE inter-  
nal data bus and can be directly accessed by the  
MCU. This enables the MCU software to load data  
into the Output Macrocells (OMC) or read data  
from both the Input and Output Macrocells (IMC  
and OMC).  
As shown in Figure 54, the CPLD has the following  
blocks:  
20 Input Macrocells (IMC)  
16 Output Macrocells (OMC)  
Macrocell Allocator  
This feature allows efficient implementation of sys-  
tem logic and eliminates the need to connect the  
data bus to the AND Array as required in most  
standard PLD macrocell architectures.  
Product Term Allocator  
Figure 56. Macrocell and I/O Port  
PRODUCT TERMS  
FROM OTHER  
MACROCELLS  
MCU ADDRESS / DATA BUS  
TO OTHER I/O PORTS  
CPLD MACROCELLS  
I/O PORTS  
DATA  
LOAD  
CONTROL  
LATCHED  
ADDRESS OUT  
PT PRESET  
MCU DATA IN  
MCU LOAD  
PRODUCT TERM  
ALLOCATOR  
I/O PIN  
DATA  
D
Q
MUX  
WR  
UP TO 10  
PRODUCT TERMS  
www.BDTIC.com/ST  
MACROCELL  
OUT TO  
MCU  
CPLD OUTPUT  
POLARITY  
SELECT  
PR DI LD  
D/T  
SELECT  
Q
PT  
CPLD  
OUTPUT  
PDR  
CLOCK  
INPUT  
D/T/JK FF  
SELECT  
COMB.  
/REG  
SELECT  
GLOBAL  
CLOCK  
MACROCELL  
CK  
TO  
I/O PORT  
ALLOC.  
CL  
CLOCK  
SELECT  
Q
DIR  
REG.  
D
WR  
PT CLEAR  
(
)
PT OUTPUT ENABLE OE  
MACROCELL FEEDBACK  
I/O PORT INPUT  
INPUT MACROCELLS  
Q
Q
D
PT INPUT LATCH GATE/CLOCK  
D
G
ALE  
AI06602  
109/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Output Macrocell (OMC)  
Eight of the Output Macrocells (OMC) are con-  
nected to Ports A and B pins and are named as  
McellAB0-McellAB7. The other eight macrocells  
are connected to Ports B and C pins and are  
named as McellBC0-McellBC7. If an McellAB out-  
put is not assigned to a specific pin in PSDsoft, the  
Macrocell Allocator block assigns it to either Port A  
or B. The same is true for a McellBC output on Port  
B or C. Table 88 shows the macrocells and port  
assignment.  
The Output Macrocell (OMC) architecture is  
shown in Figure 57. As shown in the figure, there  
are native product terms available from the AND  
Array, and borrowed product terms available (if  
unused) from other Output Macrocells (OMC). The  
polarity of the product term is controlled by the  
XOR gate. The Output Macrocell (OMC) can im-  
plement either sequential logic, using the flip-flop  
element, or combinatorial logic. The multiplexer  
selects between the sequential or combinatorial  
logic outputs. The multiplexer output can drive a  
port pin and has a feedback path to the AND Array  
inputs.  
The flip-flop in the Output Macrocell (OMC) block  
can be configured as a D, T, JK, or SR type in PS-  
Dsoft. The flip-flop’s clock, preset, and clear inputs  
may be driven from a product term of the AND Ar-  
ray. Alternatively, CLKIN (PD1) can be used for  
the clock input to the flip-flop. The flip-flop is  
clocked on the rising edge of CLKIN (PD1). The  
preset and clear are active High inputs. Each clear  
input can use up to two product terms.  
Table 88. Output Macrocell Port and Data Bit Assignments  
Port  
Output  
Macrocell  
Maximum Borrowed  
Product Terms  
Data Bit for Loading or  
Reading  
Native Product Terms  
(1)  
Assignment  
McellAB0  
McellAB1  
McellAB2  
McellAB3  
McellAB4  
McellAB5  
McellAB6  
McellAB7  
McellBC0  
Port A0, B0  
Port A1, B1  
Port A2, B2  
Port A3, B3  
Port A4, B4  
Port A5, B5  
3
3
3
3
3
3
6
6
6
6
6
6
D0  
D1  
D2  
D3  
D4  
D5  
www.BDTIC.com/ST  
Port A6, B6  
Port A7, B7  
3
3
4
6
6
5
D6  
D7  
D0  
(2)  
Port B0  
(2)  
McellBC1  
4
5
D1  
Port B1  
McellBC2  
McellBC3  
McellBC4  
McellBC5  
Port B2, C2  
Port B3, C3  
Port B4, C4  
4
4
4
4
5
5
6
6
D2  
D3  
D4  
D5  
(2)  
Port B5  
(2)  
McellBC6  
McellBC7  
4
4
6
6
D6  
D7  
Port B6  
Port B7, C7  
Note: 1. McellAB0-McellAB7 can only be assigned to Port B in the 52-pin package.  
2. Port PC0, PC1, PC5 and PC6 are assigned to JTAG pins, and are not available as macrocell outputs  
110/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Product Term Allocator  
The CPLD has a Product Term Allocator. PSDsoft  
uses the Product Term Allocator to borrow and  
place product terms from one macrocell to anoth-  
er. The following list summarizes how product  
terms are allocated:  
This is called product term expansion. PSDsoft  
Express performs this expansion as needed.  
Loading and Reading the Output Macrocells  
(OMC). The Output Macrocells (OMC) block oc-  
cupies a memory location in the MCU address  
space, as defined by the CSIOP block (see I/O  
flops in each of the 16 Output Macrocells (OMC)  
can be loaded from the data bus by a MCU. Load-  
ing the Output Macrocells (OMC) with data from  
the MCU takes priority over internal functions. As  
such, the preset, clear, and clock inputs to the flip-  
flop can be overridden by the MCU. The ability to  
load the flip-flops and read them back is useful in  
such applications as loadable counters and shift  
registers, mailboxes, and handshaking protocols.  
McellAB0-McellAB7 all have three native  
product terms and may borrow up to six more  
McellBC0-McellBC3 all have four native  
product terms and may borrow up to five more  
McellBC4-McellBC7 all have four native  
product terms and may borrow up to six more.  
Each macrocell may only borrow product terms  
from certain other macrocells. Product terms al-  
ready in use by one macrocell are not available for  
another macrocell.  
If an equation requires more product terms than  
are available to it, then “external” product terms  
are required, which consume other Output Macro-  
cells (OMC). If external product terms are used,  
extra delay is added for the equation that required  
the extra product terms.  
Data can be loaded to the Output Macrocells  
(OMC) on the trailing edge of WRITE Strobe (WR,  
edge loading) or during the time that WRITE  
Strobe (WR) is active (level loading). The method  
of loading is specified in PSDsoft Express Config-  
uration.  
Figure 57. CPLD Output Macrocell  
MASK  
REG.  
MACROCELL CS  
RD  
www.BDTIC.com/ST  
MCU DATA BUS  
[
]
D 7:0  
WR  
PT  
DIRECTION  
REGISTER  
ALLOCATOR  
(
)
ENABLE .OE  
(
)
PRESET .PR  
COMB/REG  
SELECT  
PT  
PT  
DIN PR  
LD  
MUX  
I/O PIN  
MACROCELL  
ALLOCATOR  
Q
PT  
POLARITY  
SELECT  
IN  
CLR  
PROGRAMMABLE  
PORT  
DRIVER  
(
)
CLEAR .RE  
(
)
FF D/T/JK/SR  
PT CLK  
CLKIN  
MUX  
(
)
FEEDBACK .FB  
PORT INPUT  
INPUT  
MACROCELL  
AI06617  
111/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
The OMC Mask Register. There is one Mask  
Register for each of the two groups of eight Output  
Macrocells (OMC). The Mask Registers can be  
used to block the loading of data to individual Out-  
put Macrocells (OMC). The default value for the  
Mask Registers is 00h, which allows loading of the  
Output Macrocells (OMC). When a given bit in a  
Mask Register is set to a '1,' the MCU is blocked  
from writing to the associated Output Macrocells  
(OMC). For example, suppose McellAB0-  
McellAB3 are being used for a state machine. You  
would not want a MCU write to McellAB to over-  
write the state machine registers. Therefore, you  
would want to load the Mask Register for McellAB  
(Mask Macrocell AB) with the value 0Fh.  
I/O functions. The internal node feedback can be  
routed as an input to the AND Array.  
Input Macrocells (IMC)  
The CPLD has 20 Input Macrocells (IMC), one for  
each pin on Ports A and B, and four on Port C. The  
architecture of the Input Macrocells (IMC) is  
shown in Figure 58. The Input Macrocells (IMC)  
are individually configurable, and can be used as  
a latch, register, or to pass incoming Port signals  
prior to driving them onto the PLD input bus. The  
outputs of the Input Macrocells (IMC) can be read  
by the MCU through the internal data bus.  
The enable for the latch and clock for the register  
are driven by a multiplexer whose inputs are a  
product term from the CPLD AND Array or the  
MCU Address Strobe (ALE). Each product term  
output is used to latch or clock four Input Macro-  
cells (IMC). Port inputs 3-0 can be controlled by  
one product term and 7-4 by another.  
The Output Enable of the OMC. The  
Output  
Macrocells (OMC) block can be connected to an I/  
O port pin as a PLD output. The output enable of  
each port pin driver is controlled by a single prod-  
uct term from the AND Array, ORed with the Direc-  
tion Register output. The pin is enabled upon  
Power-up if no output enable equation is defined  
and if the pin is declared as a PLD output in PSD-  
soft Express.  
Configurations for the Input Macrocells (IMC) are  
specified by equations written in PSDsoft (see Ap-  
plication Note AN1171). Outputs of the Input Mac-  
rocells (IMC) can be read by the MCU via the IMC  
buffer.  
If the Output Macrocell (OMC) output is declared  
as an internal node and not as a port pin output in  
the PSDabel file, the port pin can be used for other  
Figure 58. Input Macrocell  
[
]
www.BDTIC.com/ST  
MCU DATA BUS  
D 7:0  
_
INPUT MACROCELL RD  
DIRECTION  
REGISTER  
(
)
ENABLE .OE  
OUTPUT  
MACROCELLS BC  
PT  
AND  
MACROCELL AB  
I/O PIN  
PT  
PORT  
DRIVER  
MUX  
Q
D
PT  
ALE  
MUX  
D FF  
Q
D
G
FEEDBACK  
LATCH  
INPUT MACROCELL  
AI06603  
112/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
I/O PORTS (PSD MODULE)  
There are four programmable I/O ports: Ports A, B,  
C, and D in the PSD MODULE. Each of the ports  
is eight bits except Port D, which is 3 bits. Each  
port pin is individually user configurable, thus al-  
lowing multiple functions per port. The ports are  
configured using PSDsoft Express Configuration  
or by the MCU writing to on-chip registers in the  
CSIOP space. Port A is not available in the 52-pin  
package.  
port pin has been defined, that pin is no longer  
available for other purposes. Exceptions are not-  
ed.  
As shown in Figure 59, the ports contain an output  
multiplexer whose select signals are driven by the  
configuration bits in the Control Registers (Ports A  
and B only) and PSDsoft Express Configuration.  
Inputs to the multiplexer include the following:  
Output data from the Data Out register  
Latched address outputs  
CPLD macrocell output  
External Chip Select (ECS1-ECS2) from the  
CPLD.  
The topics discussed in this section are:  
General Port architecture  
Port operating modes  
Port Configuration Registers (PCR)  
Port Data Registers  
The Port Data Buffer (PDB) is a tri-state buffer that  
allows only one source at a time to be read. The  
Port Data Buffer (PDB) is connected to the Internal  
Data Bus for feedback and can be read by the  
MCU. The Data Out and macrocell outputs, Direc-  
tion and Control Registers, and port pin input are  
all connected to the Port Data Buffer (PDB).  
Individual Port functionality.  
General Port Architecture  
The general architecture of the I/O Port block is  
shown in Figure 59. Individual Port architectures  
64., page 121. In general, once the purpose for a  
Figure 59. General I/O Port Architecture  
DATA OUT  
REG.  
DATA OUT  
D
Q
WR  
www.BDTIC.com/ST  
ADDRESS  
ADDRESS  
PORT PIN  
D
G
Q
OUTPUT  
MUX  
ALE  
MACROCELL OUTPUTS  
EXT CS  
READ MUX  
P
D
B
OUTPUT  
SELECT  
DATA IN  
CONTROL REG.  
ENABLE OUT  
D
Q
WR  
WR  
DIR REG.  
D
Q
(
)
ENABLE PRODUCT TERM .OE  
INPUT  
MACROCELL  
CPLD-INPUT  
AI06604  
113/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
The Port pin’s tri-state output driver enable is con-  
trolled by a two input OR gate whose inputs come  
from the CPLD AND Array enable product term  
and the Direction Register. If the enable product  
term of any of the Array outputs are not defined  
and that port pin is not defined as a CPLD output  
in the PSDsoft, then the Direction Register has  
sole control of the buffer that drives the port pin.  
is configured as an output, the content of the Data  
Out Register drives the pin. When configured as  
an input, the MCU can read the port input through  
the Data In buffer. See Figure 59., page 113.  
Ports C and D do not have Control Registers, and  
are in MCU I/O Mode by default. They can be used  
for PLD I/O if equations are written for them in PS-  
Dabel.  
The contents of these registers can be altered by  
the MCU. The Port Data Buffer (PDB) feedback  
path allows the MCU to check the contents of the  
registers.  
Ports A, B, and C have embedded Input Macro-  
cells (IMC). The Input Macrocells (IMC) can be  
configured as latches, registers, or direct inputs to  
the PLDs. The latches and registers are clocked  
by Address Strobe (ALE) or a product term from  
the PLD AND Array. The outputs from the Input  
Macrocells (IMC) drive the PLD input bus and can  
PLD I/O Mode  
The PLD I/O Mode uses a port as an input to the  
CPLD’s Input Macrocells (IMC), and/or as an out-  
put from the CPLD’s Output Macrocells (OMC).  
The output can be tri-stated with a control signal.  
This output enable control signal can be defined  
by a product term from the PLD, or by resetting the  
corresponding bit in the Direction Register to '0.'  
The corresponding bit in the Direction Register  
must not be set to '1' if the pin is defined for a PLD  
input signal in PSDsoft. The PLD I/O Mode is  
specified in PSDsoft by declaring the port pins,  
and then writing an equation assigning the PLD I/  
O to a port.  
be  
read  
by  
the  
MCU.  
See  
Port Operating Modes  
The I/O Ports have several modes of operation.  
Some modes can be defined using PSDsoft, some  
by the MCU writing to the Control Registers in  
CSIOP space, and some by both. The modes that  
can only be defined using PSDsoft must be pro-  
grammed into the device and cannot be changed  
unless the device is reprogrammed. The modes  
that can be changed by the MCU can be done so  
dynamically at run-time. The PLD I/O, Data Port,  
Address Input, and Peripheral I/O Modes are the  
only modes that must be defined before program-  
ming the device. All other modes can be changed  
by the MCU at run-time. See Application Note  
AN1171 for more detail.  
Address Out Mode  
Address Out Mode can be used to drive latched  
MCU addresses on to the port pins. These port  
pins can, in turn, drive external devices. Either the  
output enable or the corresponding bits of both the  
Direction Register and Control Register must be  
set to a '1' for pins to use Address Out Mode. This  
must be done by the MCU at run-time. See Table  
91., page 115 for the address output pin assign-  
ments on Ports A and B for various MCUs.  
Peripheral I/O Mode  
Peripheral I/O Mode can be used to interface with  
external peripherals. In this mode, all of Port A  
serves as a tri-state, bi-directional data buffer for  
the MCU. Peripheral I/O Mode is enabled by set-  
ting Bit 7 of the VM Register to a '1.' Figure  
60., page 115 shows how Port A acts as a bi-di-  
rectional buffer for the MCU data bus if Peripheral  
I/O Mode is enabled. An equation for PSEL0 and/  
or PSEL1 must be written in PSDsoft. The buffer is  
tri-stated when PSEL0 or PSEL1 is low (not ac-  
tive). The PSEN signal should be “ANDed” in the  
PSEL equations to disable the buffer when PSEL  
resides in the data space.  
Table 89., page 115 summarizes which modes  
are available on each port. Table 92., page 116  
shows how and where the different modes are  
configured. Each of the port operating modes are  
described in the following sections.  
MCU I/O Mode  
In the MCU I/O Mode, the MCU uses the I/O Ports  
block to expand its own I/O ports. By setting up the  
CSIOP space, the ports on the PSD MODULE are  
mapped into the MCU address space. The ad-  
dresses of the ports are listed in Table  
A port pin can be put into MCU I/O Mode by writing  
a '0' to the corresponding bit in the Control Regis-  
ter. The MCU I/O direction may be changed by  
writing to the corresponding bit in the Direction  
Register, or by the output enable product term.  
See Peripheral I/O Mode, page 114. When the pin  
JTAG In-System Programming (ISP)  
Port C is JTAG compliant, and can be used for In-  
System Programming (ISP). For more information  
on the JTAG Port, see PROGRAMMING IN-CIR-  
114/163  
 
           
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 60. Peripheral I/O Mode  
RD  
PSEL0  
PSEL  
PSEL1  
D0-D7  
DATA BUS  
VM REGISTER BIT 7  
PA0-PA7  
WR  
AI02886  
Table 89. Port Operating Modes  
(2)  
Port Mode  
MCU I/O  
Port B  
Port C  
Port D  
Port A  
Yes  
Yes  
Yes  
No  
Yes  
PLD I/O  
McellAB Outputs  
McellBC Outputs  
Additional Ext. CS Outputs No  
PLD Inputs  
Address Out  
Peripheral I/O  
JTAG ISP  
Yes  
No  
Yes  
Yes  
No  
No  
No  
Yes  
Yes  
(3)  
Yes  
No  
Yes  
Yes  
Yes  
Yes (A7 – 0)  
Yes  
Yes (A7 – 0)  
No  
No  
No  
No  
No  
www.BDTIC.com/ST  
(1)  
No  
No  
No  
Yes  
Note: 1. JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins.  
2. Port A is not available in the 52-pin package.  
3. On pins PC2, PC3, PC4 and PC7 only.  
Table 90. Port Operating Mode Settings  
Control Register  
Setting  
Direction Register  
Setting  
Mode  
MCU I/O  
Defined in PSDsoft  
VM Register Setting  
1 = output,  
0 = input (Note 1)  
Declare pins only  
Logic equations  
Declare pins only  
0
N/A  
N/A  
N/A  
PLD I/O  
N/A  
1
(Note 1)  
Address Out  
(Port A,B)  
1 (Note 1)  
Peripheral I/O  
(Port A)  
Logic equations  
(PSEL0 & 1)  
N/A  
N/A  
PIO Bit = 1  
Note: N/A = Not Applicable  
Note: 1. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product  
term (.oe) from the CPLD AND Array.  
Table 91. I/O Port Latched Address Output Assignments  
Port A (PA3-PA0)  
Address a3-a0  
Port A (PA7-PA4)  
Address a7-a4  
Port B (PB3-PB0)  
Address a3-a0  
Port B (PB7-PB4)  
Address a7-a4  
115/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Port Configuration Registers (PCR)  
Each Port has a set of Port Configuration Regis-  
ters (PCR) used for configuration. The contents of  
the registers can be accessed by the MCU through  
normal READ/WRITE bus cycles at the addresses  
given in Table 81., page 92. The addresses in Ta-  
ble 81 are the offsets in hexadecimal from the  
base of the CSIOP register.  
The pins of a port are individually configurable and  
each bit in the register controls its respective pin.  
For example, Bit 0 in a register refers to Bit 0 of its  
port. The three Port Configuration Registers  
(PCR), shown in Table 92, are used for setting the  
Port configurations. The default Power-up state for  
each register in Table 92 is 00h.  
Note: The slew rate is a measurement of the rise  
and fall times of an output. A higher slew rate  
means a faster output response and may create  
more electrical noise. A pin operates in a high slew  
rate when the corresponding bit in the Drive Reg-  
ister is set to '1.' The default rate is slow slew.  
Table 96., page 117 shows the Drive Register for  
Ports A, B, C, and D. It summarizes which pins can  
be configured as Open Drain outputs and which  
pins the slew rate can be set for.  
Table 92. Port Configuration Registers (PCR)  
Register Name  
Control  
Port  
MCU Access  
WRITE/READ  
WRITE/READ  
WRITE/READ  
Control Register. Any bit reset to '0' in the Con-  
trol Register sets the corresponding port pin to  
MCU I/O Mode, and a '1' sets it to Address Out  
Mode. The default mode is MCU I/O. Only Ports A  
and B have an associated Control Register.  
A,B  
Direction  
A,B,C,D  
A,B,C,D  
(1)  
Drive Select  
Note: 1. See Table 96., page 117 for Drive Register Bit definition.  
Direction Register. The Direction Register, in  
conjunction with the output enable (except for Port  
D), controls the direction of data flow in the I/O  
Ports. Any bit set to '1' in the Direction Register  
causes the corresponding pin to be an output, and  
any bit set to '0' causes it to be an input. The de-  
fault mode for all port pins is input.  
show the Port Architecture diagrams for Ports A/B  
and C, respectively. The direction of data flow for  
Table 93. Port Pin Direction Control, Output  
Enable P.T. Not Defined  
Direction Register Bit  
Port Pin Mode  
0
1
Input  
Output  
Ports A, B, and C are controlled not only by the di-  
Table 94. Port Pin Direction Control, Output  
Enable P.T. Defined  
rection register, but also by the output enable  
product term from the PLD AND Array. If the out-  
put enable product term is not active, the Direction  
Register has sole control of a given pin’s direction.  
Direction  
Output Enable  
P.T.  
Port Pin Mode  
Register Bit  
0
0
1
1
0
Input  
An example of a configuration for a Port with the  
three least significant bits set to output and the re-  
mainder set to input is shown in Table 95. Since  
Port D only contains two pins (shown in Figure  
64., page 121), the Direction Register for Port D  
has only two bits active.  
1
0
1
Output  
Output  
Output  
Drive Select Register. The Drive Select Register  
configures the pin driver as Open Drain or CMOS  
for some port pins, and controls the slew rate for  
the other port pins. An external pull-up resistor  
should be used for pins configured as Open Drain.  
Table 95. Port Direction Assignment Example  
Bit 7 Bit6 Bit 5 Bit4 Bit 3 Bit2 Bit 1 Bit 0  
0
0
0
0
0
1
1
1
A pin can be configured as Open Drain if its corre-  
sponding bit in the Drive Select Register is set to a  
'1.' The default pin drive is CMOS.  
116/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Port Data Registers  
The Port Data Registers, shown in Table 97, are  
used by the MCU to write data to or read data from  
the ports. Table 97 shows the register name, the  
ports having each register type, and MCU access  
for each register type. The registers are described  
below.  
Data In. Port pins are connected directly to the  
Data In buffer. In MCU I/O Input Mode, the pin in-  
put is read through the Data In buffer.  
Register Bits are not set, writing to the macrocell  
loads data to the macrocell flip-flops. See  
OMC Mask Register. Each OMC Mask Register  
Bit corresponds to an Output Macrocell (OMC) flip-  
flop. When the OMC Mask Register Bit is set to a  
'1,' loading data into the Output Macrocell (OMC)  
flip-flop is blocked. The default value is '0' or un-  
blocked.  
Data Out Register. Stores output data written by  
the MCU in the MCU I/O Output Mode. The con-  
tents of the Register are driven out to the pins if the  
Direction Register or the output enable product  
term is set to '1.' The contents of the register can  
also be read back by the MCU.  
Output Macrocells (OMC). The CPLD Output  
Macrocells (OMC) occupy a location in the MCU’s  
address space. The MCU can read the output of  
the Output Macrocells (OMC). If the OMC Mask  
Input Macrocells (IMC). The Input Macrocells  
(IMC) can be used to latch or store external inputs.  
The outputs of the Input Macrocells (IMC) are rout-  
ed to the PLD input bus, and can be read by the  
MCU. See PLDs, page 106.  
Enable Out. The Enable Out register can be read  
by the MCU. It contains the output enable values  
for a given port. A '1' indicates the driver is in out-  
put mode. A '0' indicates the driver is in tri-state  
and the pin is in input mode.  
Table 96. Drive Register Pin Assignment  
Drive  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Open  
Bit 3  
Slew  
Bit 2  
Slew  
Bit 1  
Slew  
Bit 0  
Slew  
Register  
Open  
Drain  
Open  
Drain  
Open  
Drain  
Port A  
Drain  
Rate  
Rate  
Rate  
Rate  
Open  
Drain  
Open  
Drain  
Open  
Drain  
Open  
Drain  
Slew  
Rate  
Slew  
Rate  
Slew  
Rate  
Slew  
Rate  
Port B  
Port C  
Port D  
www.BDTIC.com/ST  
Open  
Drain  
Open  
Drain  
Open  
Drain  
Open  
Drain  
(1)  
(1)  
(1)  
(1)  
NA  
NA  
NA  
NA  
Slew  
Rate  
Slew  
Rate  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
NA  
NA  
NA  
NA  
NA  
NA  
Note: 1. NA = Not Applicable.  
Table 97. Port Data Registers  
Register Name  
Data In  
Port  
A,B,C,D  
MCU Access  
READ – input on pin  
WRITE/READ  
Data Out  
A,B,C,D  
A,B,C  
READ – outputs of macrocells  
WRITE – loading macrocells flip-flop  
Output Macrocell  
Mask Macrocell  
WRITE/READ – prevents loading into a given  
macrocell  
A,B,C  
Input Macrocell  
Enable Out  
A,B,C  
A,B,C  
READ – outputs of the Input Macrocells  
READ – the output enable control of the port driver  
117/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Ports A and B – Functionality and Structure  
Ports A and B have similar functionality and struc-  
ture, as shown in Figure 61. The two ports can be  
configured to perform one or more of the following  
functions:  
CPLD Input – Via the Input Macrocells (IMC).  
Latched Address output – Provide latched  
address output as per Table 91., page 115.  
Open Drain/Slew Rate – pins PA3-PA0 and  
PB3-PB0 can be configured to fast slew rate,  
pins PA7-PA4 and PB7-PB4 can be  
configured to Open Drain Mode.  
Peripheral Mode – Port A only (80-pin  
package)  
MCU I/O Mode  
CPLD Output – Macrocells McellAB7-  
McellAB0 can be connected to Port A or Port  
B. McellBC7-McellBC0 can be connected to  
Port B or Port C.  
Figure 61. Port A and Port B Structure  
DATA OUT  
REG.  
DATA OUT  
D
Q
WR  
PORT  
A OR B PIN  
ADDRESS  
ALE  
ADDRESS  
D
G
Q
[
]
A 7:0  
OUTPUT  
MUX  
MACROCELL OUTPUTS  
READ MUX  
P
D
B
OUTPUT  
SELECT  
DATA IN  
CONTROL REG.  
www.BDTIC.com/ST  
ENABLE OUT  
D
Q
WR  
DIR REG.  
D
Q
WR  
(
)
ENABLE PRODUCT TERM .OE  
CPLD-INPUT  
INPUT  
MACROCELL  
AI06605  
118/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Port C – Functionality and Structure  
Port C can be configured to perform one or more  
of the following functions (see Figure 62):  
Open Drain – Port C pins can be configured in  
Open Drain Mode  
Battery Backup features – PC2 can be  
MCU I/O Mode  
configured for a battery input supply, Voltage  
CPLD Output – McellBC7-McellBC0 outputs  
can be connected to Port B or Port C.  
Standby (V ).  
STBY  
PC4 can be configured as a Battery-on  
Indicator (V ), indicating when V is  
CPLD Input – via the Input Macrocells (IMC)  
BATON  
CC  
In-System Programming (ISP) – JTAG pins  
(TMS, TCK, TDI, TDO) are dedicated pins for  
device programming. (See PROGRAMMING  
INTERFACE, page 127, for more information  
on JTAG programming.)  
less than V  
.
BAT  
Port C does not support Address Out Mode, and  
therefore no Control Register is required.  
Figure 62. Port C Structure  
DATA OUT  
REG.  
DATA OUT  
D
Q
WR  
PORT C PIN  
1
SPECIAL FUNCTION  
OUTPUT  
MUX  
[
]
MCELLBC 7:0  
READ MUX  
P
D
B
OUTPUT  
SELECT  
DATA IN  
www.BDTIC.com/ST  
Q
ENABLE OUT  
DIR REG.  
D
WR  
(
)
ENABLE PRODUCT TERM .OE  
INPUT  
MACROCELL  
1
SPECIAL FUNCTION  
CPLD-INPUT  
CONFIGURATION  
BIT  
AI06618  
Note: 1. ISP or battery back-up  
119/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Port D – Functionality and Structure  
Port D has two I/O pins (only one pin, PD1, in the  
52-pin package). See Figure 63 and Figure  
64., page 121. This port does not support Address  
Out Mode, and therefore no Control Register is re-  
quired. Of the eight bits in the Port D registers,  
only Bits 2 and 1 are used to configure pins PD2  
and PD1.  
CPLD Input – direct input to the CPLD, no  
Input Macrocells (IMC)  
Slew rate – pins can be set up for fast slew  
rate  
Port D pins can be configured in PSDsoft Express  
as input pins for other dedicated functions:  
CLKIN (PD1) as input to the macrocells flip-  
flops and APD counter  
PSD Chip Select Input (CSI, PD2). Driving this  
signal High disables the Flash memory, SRAM  
and CSIOP.  
Port D can be configured to perform one or more  
of the following functions:  
MCU I/O Mode  
CPLD Output – External Chip Select (ECS1-  
ECS2)  
Figure 63. Port D Structure  
DATA OUT  
REG.  
DATA OUT  
D
Q
WR  
PORT D PIN  
OUTPUT  
MUX  
[
]
ECS 2:1  
READ MUX  
P
OUTPUT  
www.BDTIC.com/ST  
SELECT  
D
DATA IN  
B
ENABLE PRODUCT  
TERM (.OE)  
DIR REG.  
D
Q
WR  
CPLD-INPUT  
AI06606  
120/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
External Chip Select  
The CPLD also provides two External Chip Select  
(ECS1-ECS2) outputs on Port D pins that can be  
used to select external devices. Each External  
Chip Select (ECS1-ECS2) consists of one product  
term that can be configured active High or Low.  
The output enable of the pin is controlled by either  
the output enable product term or the Direction  
Register. (See Figure 64.)  
Figure 64. Port D External Chip Select Signals  
ENABLE (.OE)  
DIRECTION  
REGISTER  
PD1 PIN  
ECS1  
PT1  
POLARITY  
BIT  
ENABLE (.OE)  
DIRECTION  
REGISTER  
www.BDTIC.com/ST  
POLARITY  
BIT  
PD2 PIN  
PT2  
ECS2  
AI06607  
121/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
POWER MANAGEMENT  
All PSD MODULE offers configurable power sav-  
ing options. These options may be used individu-  
ally or in combinations, as follows:  
Once in Power-down Mode, all address/data  
signals are blocked from reaching memory  
and PLDs, and the memories are deselected  
internally. This allows the memory and PLDs  
to remain in Standby Mode even if the  
address/data signals are changing state  
externally (noise, other devices on the MCU  
bus, etc.). Keep in mind that any unblocked  
PLD input signals that are changing states  
keeps the PLD out of Standby Mode, but not  
the memories.  
PSD Chip Select Input (CSI, PD2) can be  
used to disable the internal memories, placing  
them in Standby Mode even if inputs are  
changing. This feature does not block any  
internal signals or disable the PLDs. This is a  
good alternative to using the APD Unit. There  
is a slight penalty in memory access time  
when PSD Chip Select Input (CSI, PD2)  
makes its initial transition from deselected to  
selected.  
The primary and secondary Flash memory,  
and SRAM blocks are built with power  
management technology. In addition to using  
special silicon design methodology, power  
management technology puts the memories  
into Standby Mode when address/data inputs  
are not changing (zero DC current). As soon  
as a transition occurs on an input, the affected  
memory “wakes up,” changes and latches its  
outputs, then goes back to standby. The  
designer does not have to do anything special  
to achieve Memory Standby Mode when no  
inputs are changing—it happens  
automatically.  
The PLD sections can also achieve Standby  
Mode when its inputs are not changing, as  
described in the sections on the Power  
Management Mode Registers (PMMR).  
The PMMRs can be written by the MCU at run-  
time to manage power. The PSD MODULE  
supports “blocking bits” in these registers that  
are set to block designated signals from  
reaching both PLDs. Current consumption of  
the PLDs is directly related to the composite  
frequency of the changes on their inputs (see  
Figure 68 and Figure 69., page 128).  
As with the Power Management Mode, the  
Automatic Power Down (APD) block allows  
the PSD MODULE to reduce to standby  
current automatically. The APD Unit can also  
block MCU address/data signals from  
reaching the memories and PLDs. The APD  
Unit is described in more detail in POWER  
Significant power savings can be achieved by  
blocking signals that are not used in DPLD or  
CPLD logic equations.  
Built in logic monitors the Address Strobe of  
the MCU for activity. If there is no activity for a  
certain time period (MCU is asleep), the APD  
Unit initiates Power-down Mode (if enabled).  
Figure 65. APD Unit  
APD EN  
PMMR0 BIT 1=1  
TRANSITION  
DETECTION  
DISABLE BUS  
INTERFACE  
ALE  
PD  
CLR  
APD  
CSIOP SELECT  
FLASH SELECT  
COUNTER  
RESET  
EDGE  
DETECT  
PD  
CSI  
PLD  
SRAM SELECT  
POWER DOWN  
CLKIN  
(
)
PDN SELECT  
DISABLE  
FLASH/SRAM  
AI06608  
122/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
The PSD MODULE has a Turbo Bit in PMMR0.  
This bit can be set to turn the Turbo Mode off (the  
default is with Turbo Mode turned on). While Turbo  
Mode is off, the PLDs can achieve standby current  
when no PLD inputs are changing (zero DC cur-  
rent). Even when inputs do change, significant  
power can be saved at lower frequencies (AC cur-  
rent), compared to when Turbo Mode is on. When  
the Turbo Mode is on, there is a significant DC cur-  
rent component and the AC component is higher.  
Typical standby current is of the order of  
microamperes. These standby current values  
assume that there are no transitions on any  
PLD input.  
Other Power Saving Options. The PSD MOD-  
ULE offers other reduced power saving options  
that are independent of the Power-down Mode.  
Except for the SRAM Standby and PSD Chip Se-  
lect Input (CSI, PD2) features, they are enabled by  
setting bits in PMMR0 and PMMR2.  
Automatic Power-down (APD) Unit and Power-  
down Mode. The APD Unit, shown in Figure  
65., page 122, puts the PSD MODULE into Pow-  
er-down Mode by monitoring the activity of Ad-  
dress Strobe (ALE). If the APD Unit is enabled, as  
soon as activity on Address Strobe (ALE) stops, a  
four-bit counter starts counting. If Address Strobe  
(ALE/AS, PD0) remains inactive for fifteen clock  
periods of CLKIN (PD1), Power-down (PDN) goes  
High, and the PSD MODULE enters Power-down  
Mode, as discussed next.  
Figure 66. Enable Power-down Flow Chart  
RESET  
Enable APD  
Set PMMR0 Bit 1 = 1  
Power-down Mode. By default, if you enable the  
APD Unit, Power-down Mode is automatically en-  
abled. The device enters Power-down Mode if Ad-  
dress Strobe (ALE) remains inactive for fifteen  
periods of CLKIN (PD1).  
OPTIONAL  
Disable desired inputs to PLD  
by setting PMMR0 bits 4 and 5  
and PMMR2 bits 2 through 6.  
The following should be kept in mind when the  
PSD MODULE is in Power-down Mode:  
If Address Strobe (ALE) starts pulsing again,  
the PSD MODULE returns to normal  
Operating mode. The PSD MODULE also  
returns to normal Operating mode if either  
PSD Chip Select Input (CSI, PD2) is Low or  
the RESET input is High.  
ALE idle  
for 15 CLKIN  
clocks?  
No  
www.BDTIC.com/ST  
Yes  
The MCU address/data bus is blocked from all  
memory and PLDs.  
Various signals can be blocked (prior to  
Power-down Mode) from entering the PLDs by  
setting the appropriate bits in the PMMR  
registers. The blocked signals include MCU  
control signals and the common CLKIN (PD1).  
Note: Blocking CLKIN (PD1) from the PLDs  
does not block CLKIN (PD1) from the APD  
Unit.  
PSD Module in Power  
Down Mode  
AI06609  
Table 98. Power-down Mode’s Effect on Ports  
Port Function  
MCU I/O  
Pin Level  
No Change  
All memories enter Standby Mode and are  
drawing standby current. However, the PLD  
and I/O ports blocks do not go into Standby  
Mode because you don’t want to have to wait  
for the logic and I/O to “wake-up” before their  
outputs can change. See Table 98 for Power-  
down Mode effects on PSD MODULE ports.  
PLD Out  
No Change  
Undefined  
Tri-State  
Address Out  
Peripheral I/O  
123/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
PLD Power Management  
PSD Chip Select Input (CSI, PD2)  
The power and speed of the PLDs are controlled  
by the Turbo Bit (Bit 3) in PMMR0 (see Table 99).  
By setting the bit to '1,' the Turbo Mode is off and  
the PLDs consume the specified standby current  
when the inputs are not switching for an extended  
time of 70ns. The propagation delay time is in-  
creased by 10ns (for a 5V device) after the Turbo  
Bit is set to '1' (turned off) when the inputs change  
at a composite frequency of less than 15MHz.  
When the Turbo Bit is reset to '0' (turned on), the  
PLDs run at full power and speed. The Turbo Bit  
affects the PLD’s DC power, AC power, and prop-  
agation delay. When the Turbo Mode is off, the  
uPSD3200 input clock frequency is reduced by  
5MHz from the maximum rated clock frequency.  
Blocking MCU control signals with the bits of  
PMMR2 (see Table 100., page 125) can further  
reduce PLD AC power consumption.  
SRAM Standby Mode (Battery Backup). The  
SRAM in the PSD MODULE supports a battery  
backup mode in which the contents are retained in  
the event of a power loss. The SRAM has Voltage  
PD2 of Port D can be configured in PSDsoft Ex-  
press as PSD Chip Select Input (CSI). When Low,  
the signal selects and enables the PSD MODULE  
Flash memory, SRAM, and I/O blocks for READ or  
WRITE operations. A High on PSD Chip Select In-  
put (CSI, PD2) disables the Flash memory, and  
SRAM, and reduces power consumption. Howev-  
er, the PLD and I/O signals remain operational  
when PSD Chip Select Input (CSI, PD2) is High.  
Input Clock  
CLKIN (PD1) can be turned off, to the PLD to save  
AC power consumption. CLKIN (PD1) is an input  
to the PLD AND Array and the Output Macrocells  
(OMC).  
During Power-down Mode, or, if CLKIN (PD1) is  
not being used as part of the PLD logic equation,  
the clock should be disabled to save AC power.  
CLKIN (PD1) is disconnected from the PLD AND  
Array or the Macrocells block by setting Bits 4 or 5  
to a '1' in PMMR0.  
Input Control Signals  
The PSD MODULE provides the option to turn off  
the MCU signals (WR, RD, PSEN, and Address  
Strobe (ALE)) to the PLD to save AC power con-  
sumption (see Table 101., page 125). These con-  
trol signals are inputs to the PLD AND Array.  
During Power-down Mode, or, if any of them are  
not being used as part of the PLD logic equation,  
these control signals should be disabled to save  
Standby (V  
external battery. When V  
, PC2) that can be connected to an  
STBY  
becomes lower than  
CC  
V
then the SRAM automatically connects to  
STBY  
Voltage Standby (V  
The SRAM Standby Current (I  
µA. The SRAM data retention voltage is 2V mini-  
mum. The Battery-on Indicator (V ) can be  
routed to PC4. This signal indicates when the V  
, PC2) as a power source.  
STBY  
) is typically 0.5  
STBY  
BATON  
CC  
www.BDTIC.com/ST  
AC power. They are disconnected from the PLD  
AND Array by setting Bits 2, 3, 4, 5, and 6 to a '1'  
in PMMR2.  
has dropped below V  
.
STBY  
Table 99. Power Management Mode Registers PMMR0  
Bit 0  
Bit 1  
Bit 2  
X
0
Not used, and should be set to zero.  
0 = off Automatic Power-down (APD) is disabled.  
1 = on Automatic Power-down (APD) is enabled.  
APD Enable  
X
0
Not used, and should be set to zero.  
0 = on PLD Turbo Mode is on  
Bit 3  
PLD Turbo  
PLD Turbo Mode is off, saving power.  
uPSD3200 operates at 5MHz below the maximum rated clock frequency  
1 = off  
0 = on  
CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN  
(PD1) Powers-up the PLD when Turbo Bit is '0.'  
Bit 4  
Bit 5  
PLD Array clk  
PLD MCell clk  
1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.  
0 = on CLKIN (PD1) input to the PLD macrocells is connected.  
1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.  
Bit 6  
Bit 7  
X
X
0
0
Not used, and should be set to zero.  
Not used, and should be set to zero.  
124/163  
 
         
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 100. Power Management Mode Registers PMMR2  
Bit 0  
Bit 1  
X
X
0
0
Not used, and should be set to zero.  
Not used, and should be set to zero.  
0 = on WR input to the PLD AND Array is connected.  
PLD Array  
WR  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
1 = off WR input to PLD AND Array is disconnected, saving power.  
0 = on RD input to the PLD AND Array is connected.  
PLD Array  
RD  
1 = off RD input to PLD AND Array is disconnected, saving power.  
0 = on PSEN input to the PLD AND Array is connected.  
1 = off PSEN input to PLD AND Array is disconnected, saving power.  
0 = on ALE input to the PLD AND Array is connected.  
PLD Array  
PSEN  
PLD Array  
ALE  
1 = off ALE input to PLD AND Array is disconnected, saving power.  
Bit 6  
Bit 7  
X
X
0
0
Not used, and should be set to zero.  
Not used, and should be set to zero.  
Note: The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers.  
Table 101. APD Counter Operation  
APD Enable Bit  
ALE Level  
X
APD Counter  
0
1
1
Not Counting  
Not Counting  
Pulsing  
0 or 1  
Counting (Generates PDN after 15 Clocks)  
www.BDTIC.com/ST  
125/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
RESET TIMING AND DEVICE STATUS AT RESET  
Upon Power-up, the PSD MODULE requires a Re-  
Warm RESET  
set (RESET) pulse of duration t after V  
NLNH-PO  
CC  
Once the device is up and running, the PSD MOD-  
ULE can be reset with a pulse of a much shorter  
is steady. During this period, the device loads in-  
ternal configurations, clears some of the registers  
and sets the Flash memory into operating mode.  
After the rising edge of Reset (RESET), the PSD  
MODULE remains in the Reset Mode for an addi-  
duration, t  
. The same t  
period is needed  
NLNH  
OPR  
before the device is operational after a Warm RE-  
SET. Figure 67 shows the timing of the Power-up  
and Warm RESET.  
tional period, t  
is allowed.  
, before the first memory access  
OPR  
I/O Pin, Register and PLD Status at RESET  
Table 102 shows the I/O pin, register and PLD sta-  
tus during Power-on RESET, Warm RESET, and  
Power-down Mode. PLD outputs are always valid  
during Warm RESET, and they are valid in Power-  
on RESET once the internal Configuration bits are  
loaded. This loading is completed typically long  
The Flash memory is reset to the READ Mode  
upon Power-up. Sector Select (FS0-FS3 and  
CSBOOT0-CSBOOT1) must all be Low, WRITE  
Strobe (WR, CNTL0) High, during Power-on  
RESET for maximum security of the data contents  
and to remove the possibility of a byte being writ-  
ten on the first edge of WRITE Strobe (WR). Any  
Flash memory WRITE cycle initiation is prevented  
before the V ramps up to operating level. Once  
CC  
the PLD is active, the state of the outputs are de-  
termined by the PLD equations.  
automatically when V is below V  
.
CC  
LKO  
Figure 67. Reset (RESET) Timing  
VCC(min)  
VCC  
t
t
OPR  
t
t
NLNH-PO  
NLNH  
Warm Reset  
OPR  
Power-On Reset  
RESET  
www.BDTIC.com/ST  
Table 102. Status During Power-on RESET, Warm RESET and Power-down Mode  
AI07437  
Port Configuration  
MCU I/O  
Power-on RESET  
Input mode  
Warm RESET  
Input mode  
Power-down Mode  
Unchanged  
Valid after internal PSD  
configuration bits are  
loaded  
Depends on inputs to PLD  
(addresses are blocked in  
PD Mode)  
PLD Output  
Valid  
Address Out  
Tri-stated  
Tri-stated  
Tri-stated  
Tri-stated  
Not defined  
Tri-stated  
Peripheral I/O  
Register  
Power-on RESET  
Warm RESET  
Power-down Mode  
PMMR0 and PMMR2  
Cleared to '0'  
Unchanged  
Unchanged  
Cleared to '0' by internal  
Power-on RESET  
Depends on .re and .pr  
equations  
Depends on .re and .pr  
equations  
Macrocells flip-flop status  
Initialized, based on the  
selection in PSDsoft  
Configuration menu  
Initialized, based on the  
selection in PSDsoft  
Configuration menu  
(1)  
Unchanged  
Unchanged  
VM Register  
All other registers  
Cleared to '0'  
Cleared to '0'  
Note: 1. The SR_cod and PeriphMode Bits in the VM Register are always cleared to '0' on Power-on RESET or Warm RESET.  
126/163  
 
         
uPSD3212A, uPSD3212C, uPSD3212CV  
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE  
The JTAG Serial Interface pins (TMS, TCK, TDI,  
TDO) are dedicated pins on Port C (see Table  
103). All memory blocks (primary and secondary  
Flash memory), PLD logic, and PSD MODULE  
Configuration Register Bits may be programmed  
through the JTAG Serial Interface block. A blank  
device can be mounted on a printed circuit board  
and programmed using JTAG.  
The standard JTAG signals (IEEE 1149.1) are  
TMS, TCK, TDI, and TDO. Two additional signals,  
TSTAT and TERR, are optional JTAG extensions  
used to speed up Program and Erase cycles.  
JTAG Extensions  
TSTAT and TERR are two JTAG extension signals  
enabled by an “ISC_ENABLE” command received  
over the four standard JTAG signals (TMS, TCK,  
TDI, and TDO). They are used to speed Program  
and Erase cycles by indicating status on uPDS  
signals instead of having to scan the status out se-  
rially using the standard JTAG channel. See Appli-  
cation Note AN1153.  
TERR indicates if an error has occurred when  
erasing a sector or programming a byte in Flash  
memory. This signal goes Low (active) when an  
Error condition occurs, and stays Low until an  
“ISC_CLEAR” command is executed or a chip Re-  
set (RESET) pulse is received after an  
“ISC_DISABLE” command.  
By default, on a blank device (as shipped from the  
factory or after erasure), four pins on Port C are  
the basic JTAG signals TMS, TCK, TDI, and TDO.  
Standard JTAG Signals  
TSTAT behaves the same as Ready/Busy de-  
scribed in Ready/Busy (PC3), page 93. TSTAT is  
High when the PSD MODULE device is in READ  
Mode (primary and secondary Flash memory con-  
tents can be read). TSTAT is Low when Flash  
memory Program or Erase cycles are in progress,  
and also when data is being written to the second-  
ary Flash memory.  
At power-up, the standard JTAG pins are inputs,  
waiting for a JTAG serial command from an exter-  
nal JTAG controller device (such as FlashLINK or  
Automated Test Equipment). When the enabling  
command is received, TDO becomes an output  
and the JTAG channel is fully functional. The  
same command that enables the JTAG channel  
may optionally enable the two additional JTAG sig-  
nals, TSTAT and TERR.  
The RESET input to the uPS3200 should be active  
during JTAG programming. The active RESET  
puts the MCU module into RESET Mode while the  
PSD Module is being programmed. See Applica-  
TSTAT and TERR can be configured as “open  
drain” type signals during an “ISC_ENABLE” com-  
mand.  
Security and Flash memory Protection  
When the Security Bit is set, the device cannot be  
read on a Device Programmer or through the  
JTAG Port. When using the JTAG Port, only a Full  
Chip Erase command is allowed.  
www.BDTIC.com/ST  
tion Note AN1153 for more details on JTAG In-  
System Programming (ISP).  
The uPSD321x Devices supports JTAG In-Sys-  
tem-Configuration (ISC) commands, but not  
Boundary Scan. The PSDsoft Express software  
tool and FlashLINK JTAG programming cable im-  
plement the JTAG In-System-Configuration (ISC)  
commands.  
All other Program, Erase and Verify commands  
are blocked. Full Chip Erase returns the part to a  
non-secured blank state. The Security Bit can be  
set in PSDsoft Express Configuration.  
All primary and secondary Flash memory sectors  
can individually be sector protected against era-  
sures. The sector protect bits can be set in PSD-  
soft Express Configuration.  
Table 103. JTAG Port Signals  
Port C Pin  
PC0  
JTAG Signals  
TMS  
Description  
Mode Select  
INITIAL DELIVERY STATE  
PC1  
PC3  
PC4  
PC5  
PC6  
TCK  
Clock  
When delivered from ST, the uPSD321x Devices  
have all bits in the memory and PLDs set to '1.'  
The code, configuration, and PLD logic are loaded  
using the programming procedure. Information for  
programming the device is available directly from  
ST. Please contact your local sales representa-  
tive.  
TSTAT  
TERR  
TDI  
Status (optional)  
Error Flag (optional)  
Serial Data In  
Serial Data Out  
TDO  
127/163  
 
           
uPSD3212A, uPSD3212C, uPSD3212CV  
AC/DC PARAMETERS  
These tables describe the AD and DC parameters  
of the uPSD321x Devices:  
The following are issues concerning the parame-  
ters presented:  
DC Electrical Specification  
AC Timing Specification  
In the DC specification the supply current is  
given for different modes of operation.  
The AC power component gives the PLD,  
Flash memory, and SRAM mA/MHz  
specification. Figures 68 and 69 show the PLD  
mA/MHz as a function of the number of  
Product Terms (PT) used.  
PLD Timing  
Combinatorial Timing  
Synchronous Clock Mode  
Asynchronous Clock Mode  
Input Macrocell Timing  
In the PLD timing parameters, add the  
required delay when Turbo Bit is '0.'  
MCU Module Timing  
READ Timing  
WRITE Timing  
Power-down and RESET Timing  
Figure 68. PLD I /Frequency Consumption (5V range)  
CC  
110  
100  
90  
V
CC  
= 5V  
80  
70  
60  
50  
40  
www.BDTIC.com/ST  
30  
PT 100%  
20  
PT 25%  
10  
0
0
5
10  
15  
20  
25  
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)  
AI02894  
Figure 69. PLD I /Frequency Consumption (3V range)  
CC  
60  
V
= 3V  
CC  
50  
40  
30  
20  
10  
0
PT 100%  
PT 25%  
0
5
10  
15  
20  
25  
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)  
AI03100  
128/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 104. PSD MODULE Example, Typ. Power Calculation at V = 5.0V (Turbo Mode Off)  
CC  
Conditions  
MCU Clock Frequency  
Highest Composite PLD input frequency  
(Freq PLD)  
= 12MHz  
= 8MHz  
MCU ALE frequency (Freq ALE)  
% Flash memory Access  
% SRAM access  
= 2MHz  
= 80%  
= 15%  
% I/O access  
= 5% (no additional power above base)  
Operational Modes  
% Normal  
= 40%  
= 60%  
% Power-down Mode  
Number of product terms used  
(from fitter report)  
= 45 PT  
% of total product terms  
Turbo Mode  
= 45/182 = 24.7%  
= Off  
Calculation (using typical values)  
I
total  
= I (MCUactive) x %MCUactive + I (PSDactive) x %PSDactive + I (pwrdown) x %pwrdown  
CC CC PD  
CC  
I
I
I
(MCUactive)  
= 20mA  
= 250µA  
www.BDTIC.com/ST  
CC  
(pwrdown)  
PD  
(PSDactive)  
= I (ac) + I (dc)  
CC CC  
CC  
= %flash x 2.5mA/MHz x Freq ALE  
+ %SRAM x 1.5mA/MHz x Freq ALE  
+ % PLD x (from graph using Freq PLD)  
= 0.8 x 2.5mA/MHz x 2MHz + 0.15 x 1.5mA/MHz x 2MHz + 24mA  
= (4 + 0.45 + 24) mA  
= 28.45mA  
I
total  
= 20mA x 40% + 28.45mA x 40% + 250µA x 60%  
= 8mA + 11.38mA + 150µA  
= 19.53mA  
This is the operating power with no Flash memory Erase or Program cycles in progress. Calculation is based on all I/O  
CC  
pins being disconnected and I = 0mA.  
OUT  
129/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
MAXIMUM RATING  
Stressing the device above the rating listed in the  
Absolute Maximum Ratings” table may cause per-  
manent damage to the device. These are stress  
ratings only and operation of the device at these or  
any other conditions above those indicated in the  
Operating sections of this specification is not im-  
plied. Exposure to Absolute Maximum Rating con-  
ditions for extended periods may affect device  
reliability. Refer also to the STMicroelectronics  
SURE Program and other relevant quality docu-  
ments.  
Table 105. Absolute Maximum Ratings  
Symbol  
Parameter  
Min.  
Max.  
125  
235  
6.5  
Unit  
°C  
°C  
V
T
Storage Temperature  
–65  
STG  
(1)  
T
LEAD  
Lead Temperature during Soldering (20 seconds max.)  
V
IO  
Input and Output Voltage (Q = V or Hi-Z)  
–0.5  
–0.5  
OH  
V
CC  
Supply Voltage  
6.5  
V
V
Device Programmer Supply Voltage  
–0.5  
14.0  
2000  
V
PP  
(2)  
V
ESD  
–2000  
V
Electrostatic Discharge Voltage (Human Body Model)  
Note: 1. IPC/JEDEC J-STD-020A  
2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 , R2=500 )  
www.BDTIC.com/ST  
130/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
EMC CHARACTERISTICS  
Susceptibility test are performed on a sample ba-  
sis during product characterization.  
Functional EMS (Electromagnetic  
Susceptibility)  
Based on a simple running application on the  
product (toggling 2 LEDs through I/O ports), the  
product is stressed by two electromagnetic events  
until a failure occurs (indicated by the LEDs).  
ESD. Electro-Static Discharge (positive and neg-  
ative) is applied on all pins of the device until a  
functional disturbance occurs. This test conforms  
with the IEC 1000-4-2 Standard.  
Software Recommendations. The  
flowchart must include the management of ‘run-  
away’ conditions, such as:  
software  
Corrupted program counter  
Unexpected reset  
Critical data corruption (e.g., control registers)  
Prequalification trials. Most of the common fail-  
ures (unexpected reset and program counter cor-  
ruption) can be reproduced by manually forcing a  
low state on the RESET pin or the oscillator pins  
for 1 second.  
To complete these trials, ESD stress can be ap-  
plied directly on the device over the range of spec-  
ification values. When unexpected behavior is  
detected, the software can be hardened to prevent  
unrecoverable errors occurring (see Application  
Note AN1015).  
FTB. A burst of Fast Transient voltage (positive  
and negative) is applied to V and V through a  
DD  
SS  
100pF capacitor, until a functional disturbance oc-  
curs. This test conforms with the IEC 1000-4-2  
Standard.  
A device reset allows normal operations to be re-  
sumed. The test results are given in Table 106,  
based on the EMS levels and classes defined in  
Application Note AN1709.  
Designing Hardened Software To Avoid Noise  
Problems  
EMC characterization and optimization are per-  
formed at component level with a typical applica-  
tion environment and simplified MCU software. It  
should be noted that good EMC performance is  
highly dependent on the user application and the  
Absolute Maximum Ratings (Electrical  
Sensitivity)  
Based on three different tests (ESD, LU, and DLU)  
and using specific measurement methods, the  
product is stressed in order to determine its perfor-  
mance in terms of electrical sensitivity. For more  
details, refer to the Application Note AN1181.  
Electro-Static Discharge (ESD). Electro-Static  
discharges (a positive then a negative pulse sepa-  
rated by 1 second) are applied to the pins of each  
sample according to each pin combination. The  
software in partiwcularw. w.BDTIC.com/ST  
sample size depends on the number of supply pins  
Therefore, it is recommended that the user applies  
EMC software optimization and prequalification  
tests in relation with the EMC level requested for  
the user’s application.  
in the device (3 parts*(n+1) supply pin). The Hu-  
man Body Model is simulated (see Table 107).  
This test conforms to the JESD22-A114A Stan-  
dard.  
Table 106. EMS Test Results  
Level/  
Symbol  
Parameter  
Conditions  
(1)  
Class  
V
= 4V; T = 25°C; f  
= 40MHz;  
Voltage limits to be applied on any I/O pin to  
induce a functional disturbance  
DD  
A
OSC  
V
FESD  
3C  
WDT off conforms to IEC 1000-4-2  
Note: 1. Data based on characterization results, not tested in production.  
Table 107. ESD Absolute Maximum Ratings  
(1)  
Symbol  
Parameter  
Conditions  
Unit  
Maximum Value  
Electro-static discharge voltage (Human  
Body Model)  
V
T = 25°C  
A
2000  
V
ESD(HBM)  
Note: 1. Data based on characterization results, not tested in production  
131/163  
 
           
uPSD3212A, uPSD3212C, uPSD3212CV  
LU. 3 complementary static tests are required on  
10 parts to assess the latch-up performance. A  
supply overvoltage (applied to each power supply  
pin) and a current injection (applied to each input,  
output, and configurable I/O pin) are performed on  
each sample. This test conforms to the EIA/JESD  
78 IC Latch-up Standard (see Table 108). For  
more details, refer to the Application Note,  
AN1181.  
DLU. Electro-static discharges (one positive then  
one negative test) are applied to each pin of 3  
samples when the micro is running to assess the  
latch-up performance in dynamic mode. Power  
supplies are set to the typical values, the oscillator  
is connected as near as possible to the pins of the  
micro, and the component is put in reset mode.  
This test conforms to the IEC 1000-4-2 and  
SAEJ1752/3 Standards (see Table 108). For more  
details, refer to the Application Note, AN1181.  
Table 108. Latch-up and Dynamic Latch-up Electrical Sensitivities  
Level/  
Symbol  
Parameter  
Conditions  
(1)  
Class  
T = 25°C  
LU  
Static Latch-up Class  
Dynamic Latch-up Class  
A
A
A
DLU  
V
= 5V; T = 25°C; f  
= 40MHz  
OSC  
DD  
A
Note: 1. Class description: A Class is an STMicroelectronics internal specification. All of its limits are higher than the JEDEC specifications.  
This means when a device belongs to “Class A,” it exceeds the JEDEC standard. “Class B” strictly covers all of the JEDEC criteria  
(International standards).  
www.BDTIC.com/ST  
132/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
DC AND AC PARAMETERS  
This section summarizes the operating and mea-  
surement conditions, and the DC and AC charac-  
teristics of the device. The parameters in the DC  
and AC Characteristic tables that follow are de-  
rived from tests performed under the Measure-  
ment Conditions summarized in the relevant  
tables. Designers should check that the operating  
conditions in their circuit match the measurement  
conditions when relying on the quoted parame-  
ters.  
Table 109. Operating Conditions (5V Devices)  
Symbol  
Parameter  
Min.  
4.5  
–40  
0
Max.  
5.5  
85  
Unit  
V
V
CC  
Supply Voltage  
Ambient Operating Temperature (Industrial)  
Ambient Operating Temperature (Commercial)  
°C  
°C  
T
A
70  
Table 110. Operating Conditions (3V Devices)  
Symbol  
Parameter  
Min.  
3.0  
–40  
0
Max.  
3.6  
85  
Unit  
V
V
Supply Voltage  
CC  
Ambient Operating Temperature (Industrial)  
Ambient Operating Temperature (Commercial)  
°C  
°C  
T
A
70  
Table 111. AC Signal Letter Symbols for  
Signal Letters  
Timing  
Note: Example: t  
= Time from Address Valid to ALE Invalid.  
AVLX  
A
C
D
I
Address  
Table 112. AC Signal Behavior Symbols for  
Timing  
Clock  
www.BDTIC.com/ST  
Signal Behavior  
Input Data  
Instruction  
ALE  
t
Time  
L
Logic Level Low or ALE  
Logic Level High  
Valid  
L
H
V
X
Z
N
P
Q
R
W
B
M
RESET Input or Output  
PSEN signal  
Output Data  
RD signal  
WR signal  
No Longer a Valid Logic Level  
Float  
PW  
Pulse Width  
Note: Example: t  
= Time from Address Valid to ALE Invalid.  
AVLX  
V
STBY  
Output  
Output Macrocell  
133/163  
 
     
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 70. Switching Waveforms – Key  
INPUTS  
OUTPUTS  
WAVEFORMS  
STEADY INPUT  
STEADY OUTPUT  
MAY CHANGE FROM  
HI TO LO  
WILL BE CHANGING  
FROM HI TO LO  
MAY CHANGE FROM  
LO TO HI  
WILL BE CHANGING  
LO TO HI  
DON'T CARE  
CHANGING, STATE  
UNKNOWN  
OUTPUTS ONLY  
CENTER LINE IS  
TRI-STATE  
AI03102  
www.BDTIC.com/ST  
134/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 113. Major Parameters  
Parameters/Conditions/  
Comments  
5V Test  
Conditions  
3.3V Test  
Conditions  
5.0V Value  
3.3V Value  
Unit  
Operating Voltage  
4.5 to 5.5  
–40 to 85  
3.0 to 3.6  
–40 to 85  
V
Operating Temperature  
°C  
MCU Frequency  
12MHz (min) for USB;  
1 Min, 40 Max  
1 Min, 24 Max MHz  
2
8MHz (min) for I C  
Active Current, Typical  
(25°C operation; 80% Flash and  
15% SRAM accesses, 45 PLD  
product terms used; PLD Turbo  
mode Off)  
24MHz MCU clock,  
12MHz PLD input  
frequency, 4MHz ALE  
12MHz MCU clock,  
6MHz PLD input  
frequency, 2MHz ALE  
72  
21  
7
mA  
Idle Current, Typical  
(CPU halted but some peripherals 24MHz MCU clock,  
active; 25°C operation; 45 PLD  
product terms used; PLD Turbo  
mode Off)  
12MHz MCU clock,  
1MHz PLD input  
frequency  
12MHz PLD input  
frequency  
25  
mA  
µA  
Standby Current, Typical  
(Power-down Mode, requires reset  
to exit mode; without Low-Voltage  
Detect (LVD) Supervisor)  
180µA with LVD  
110  
0.5  
100µA with LVD  
60  
SRAM Backup Current, Typical  
(If external battery is attached.)  
0.5  
µA  
V
V
= 0.25V (max);  
I
= 8 (max);  
= –2 (min)  
V
V
= 0.15V (max);  
I
= 4 (max);  
= –1 (min)  
I/O Sink/Source Current  
Ports A, B, C, and D  
OL  
OL  
OL  
OL  
mA  
= 3.9V (min)  
I
= 2.6V (min)  
I
OH  
OH  
OH  
OH  
PLD Macrocells  
(For registered or combinatorial  
logic)  
16  
www.BDTIC.com/ST  
16  
69  
PLD Inputs  
(Inputs from pins, macrocell  
feedback, or MCU addresses)  
69  
PLD Outputs  
(Output to pins or internal  
feedback)  
16  
16  
22  
PLD Propagation Delay, Typical  
(PLD input to output, Turbo Mode)  
15  
ns  
135/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 114. DC Characteristics (5V Devices)  
Test Condition  
(in addition to those  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
Input High Voltage (Ports 1, 2,  
3, 4[Bits 7,6,5,4,3,1,0], XTAL1,  
RESET)  
V
4.5V < V < 5.5V  
0.7V  
V
V
+ 0.5  
V
V
V
IH  
CC  
CC  
CC  
Input High Voltage (Ports A, B,  
C, D, 4[Bit 2])  
V
IH1  
4.5V < V < 5.5V  
+ 0.5  
2.0  
CC  
CC  
Input Low Voltage (Ports 1, 2,  
3, 4[Bits 7,6,5,4,3,1,0], XTAL1,  
RESET)  
V
4.5V < V < 5.5V  
V
V
– 0.5  
0.3V  
CC  
IL  
CC  
SS  
Input Low Voltage  
(Ports A, B, C, D)  
4.5V < V < 5.5V  
–0.5  
– 0.5  
0.8  
0.8  
0.1  
V
V
V
CC  
V
IL1  
V
OL  
Input Low Voltage  
(Port 4[Bit 2])  
4.5V < V < 5.5V  
CC  
SS  
I
= 20µA  
OL  
0.01  
0.25  
V
CC  
= 4.5V  
Output Low Voltage  
(Ports A,B,C,D)  
I
V
= 8mA  
= 4.5V  
OL  
0.45  
0.45  
0.45  
V
V
V
V
CC  
Output Low Voltage  
(Ports 1,2,3,4, WR, RD)  
V
V
I
= 1.6mA  
OL1  
OL  
Output Low Voltage  
(Port 0, ALE, PSEN)  
I
= 3.2mA  
= –20µA  
OL2  
OL  
I
OH  
4.4  
www.BDTIC.com/ST  
4.49  
V
CC  
= 4.5V  
Output High Voltage  
(Ports A,B,C,D)  
V
OH  
I
= –2mA  
OH  
2.4  
3.9  
V
V
CC  
= 4.5V  
I
= –80µA  
= –10µA  
= –800µA  
= –80µA  
= –1µA  
2.4  
4.05  
2.4  
V
V
V
V
V
V
OH  
OH  
Output High Voltage  
(Ports 1,2,3,4, WR, RD)  
V
OH1  
I
I
OH  
Output High Voltage (Port 0 in  
ext. Bus Mode, ALE, PSEN)  
V
V
OH2  
I
4.05  
OH  
Output High Voltage V  
I
V
– 0.8  
STBY  
OH3  
STBYON  
OH  
V
Low Voltage RESET  
0.1V hysteresis  
= 3.2mA  
3.75  
2.0  
4.0  
4.25  
3.0  
LVR  
XTAL Open Bias Voltage  
(XTAL1, XTAL2)  
V
I
OL  
V
OP  
V
(min) for Flash Erase and  
CC  
V
2.5  
2.0  
2
4.2  
V
V
V
LKO  
Program  
V
V
– 0.2  
CC  
SRAM (PSD) Standby Voltage  
STBY  
SRAM (PSD) Data Retention  
Voltage  
V
Only on V  
STBY  
DF  
V
= 0.45V  
Logic '0' Input Current  
(Ports 1,2,3,4)  
IN  
I
–10  
–65  
–50  
µA  
µA  
IL  
(0V for Port 4[pin 2])  
V
= 3.5V  
Logic 1-to-0 Transition Current  
(Ports 1,2,3,4)  
IN  
I
TL  
–650  
(2.5V for Port 4[pin 2])  
136/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Test Condition  
(in addition to those  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
in Table  
109., page 133)  
SRAM (PSD) Standby Current  
I
V
= 0V  
0.5  
1
µA  
µA  
µA  
µA  
STBY  
CC  
(V  
input)  
STBY  
SRAM (PSD) Idle Current  
(V input)  
I
V
> V  
–0.1  
–10  
–20  
0.1  
–55  
–50  
IDLE  
CC STBY  
STBY  
Reset Pin Pull-up Current  
(RESET)  
I
V
= V  
IN SS  
RST  
XTAL1 = V  
XTAL2 = V  
XTAL Feedback Resistor  
Current (XTAL1)  
CC  
I
FR  
SS  
I
V
< V < V  
SS IN CC  
Input Leakage Current  
Output Leakage Current  
–1  
1
µA  
µA  
LI  
I
0.45 < V  
< V  
OUT CC  
–10  
10  
LO  
V
= 5.5V  
CC  
250  
µA  
LVD logic disabled  
(1)  
Power-down Mode  
I
PD  
LVD logic enabled  
380  
30  
10  
38  
20  
62  
30  
µA  
mA  
mA  
mA  
mA  
mA  
mA  
Active (12MHz)  
Idle (12MHz)  
Active (24MHz)  
Idle (24MHz)  
Active (40MHz)  
Idle (40MHz)  
20  
8
V
CC  
V
CC  
V
CC  
= 5V  
= 5V  
= 5V  
30  
15  
40  
20  
(2,3,5)  
I
CC_CPU  
www.BDTIC.com/ST  
PLD_TURBO = Off,  
(5)  
0
µA/PT  
µA/PT  
mA  
(4)  
f = 0MHz  
PLD Only  
PLD_TURBO = On,  
400  
700  
f = 0MHz  
I
CC_PSD  
Operating  
(5)  
Supply Current  
During Flash memory  
WRITE/Erase Only  
(DC)  
15  
30  
Flash  
memory  
Read only, f = 0MHz  
f = 0MHz  
0
0
0
0
mA  
mA  
SRAM  
PLD AC Base  
Note 4  
mA/  
MHz  
I
CC_PSD  
(5)  
Flash memory AC Adder  
SRAM AC Adder  
2.5  
1.5  
3.5  
3.0  
(AC)  
mA/  
MHz  
Note: 1. I (Power-down Mode) is measured with:  
PD  
2. XTAL1=V ; XTAL2=not connected; RESET=V ; Port 0 =V ; all other pins are disconnected. PLD not in Turbo Mode.  
SS  
CC  
CC  
3. I  
(active mode) is measured with:  
CC_CPU  
4. XTAL1 driven with t  
, t  
= 5ns, V = V +0.5V, V = V – 0.5V, XTAL2 = not connected; RESET=V ; Port 0=V ; all  
CLCH CHCL IL SS IH CC SS CC  
other pins are disconnected. I would be slightly higher if a crystal oscillator is used (approximately 1mA).  
CC  
5. I  
(Idle Mode) is measured with:  
CC_CPU  
6. XTAL1 driven with t  
, t  
= 5ns, V = V +0.5V, V = V – 0.5V, XTAL2 = not connected; Port 0 = V  
;
CC  
CLCH CHCL  
IL  
SS  
IH  
CC  
7. RESET=V ; all other pins are disconnected.  
CC  
8. See Figure 68., page 128 for the PLD current calculation.  
9. I/O current = 0mA, all I/O pins are disconnected.  
137/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 115. DC Characteristics (3V Devices)  
Test Condition  
(in addition to those  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
Input High Voltage (Ports 1, 2,  
3, 4[Bits 7,6,5,4,3,1,0], A, B, C,  
D, XTAL1, RESET)  
V
3.0V < V < 3.6V  
0.7V  
V
V
+ 0.5  
V
V
V
IH  
CC  
CC  
CC  
Input High Voltage (Port 4[Bit  
2])  
V
3.0V < V < 3.6V  
+ 0.5  
2.0  
IH1  
CC  
CC  
Input High Voltage (Ports 1, 2,  
3, 4[Bits 7,6,5,4,3,1,0], XTAL1,  
RESET)  
V
3.0V < V < 3.6V  
V
V
– 0.5  
0.3V  
CC  
IL  
CC  
SS  
Input Low Voltage  
(Ports A, B, C, D)  
3.0V < V < 3.6V  
–0.5  
– 0.5  
0.8  
0.8  
0.1  
V
V
V
CC  
V
IL1  
V
OL  
Input Low Voltage  
(Port 4[Bit 2])  
3.0V < V < 3.6V  
CC  
SS  
I
= 20µA  
OL  
0.01  
0.15  
V
= 3.0V  
CC  
Output Low Voltage  
(Ports A,B,C,D)  
I
V
= 4mA  
= 3.0V  
OL  
0.45  
V
CC  
I
= 1.6mA  
= 100µA  
= 3.2mA  
= 200µA  
0.45  
0.3  
V
V
V
V
OL  
OL  
OL  
OL  
Output Low Voltage  
(Ports 1,2,3,4, WR, RD)  
V
V
OL1  
I
I
I
0.45  
Output Low Voltage  
(Port 0, ALE, PSEN)  
OL2  
0.3  
www.BDTIC.com/ST  
I
= –20µA  
OH  
2.9  
2.99  
V
V
V
= 3.0V  
CC  
Output High Voltage  
(Ports A,B,C,D)  
V
OH  
I
V
= –1mA  
OH  
2.4  
2.6  
= 3.0V  
CC  
I
= –20µA  
= –10µA  
= –800µA  
= –80µA  
= –1µA  
2.0  
2.7  
2.0  
2.7  
V
V
V
V
V
V
OH  
OH  
Output High Voltage  
(Ports 1,2,3,4, WR, RD)  
V
OH1  
I
I
OH  
Output High Voltage (Port 0 in  
ext. Bus Mode, ALE, PSEN)  
V
V
OH2  
I
OH  
Output High Voltage V  
I
V
– 0.8  
STBY  
OH3  
STBYON  
OH  
V
Low Voltage Reset  
0.1V hysteresis  
= 3.2mA  
2.3  
1.0  
2.5  
2.7  
2.0  
LVR  
XTAL Open Bias Voltage  
(XTAL1, XTAL2)  
V
I
OL  
V
OP  
V
(min) for Flash Erase and  
CC  
V
1.5  
2.0  
2
2.2  
V
V
V
LKO  
Program  
V
STBY  
V
– 0.2  
CC  
SRAM (PSD) Standby Voltage  
SRAM (PSD) Data Retention  
Voltage  
V
Only on V  
STBY  
DF  
IL  
V
IN  
= 0.45V  
Logic '0' Input Current  
(Ports 1,2,3,4)  
I
–1  
–50  
µA  
(0V for Port 4[pin 2])  
138/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Test Condition  
(in addition to those  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
in Table  
110., page 133)  
V
= 3.5V  
Logic 1-to-0 Transition Current  
(Ports 1,2,3,4)  
IN  
I
–25  
–250  
1
µA  
µA  
µA  
µA  
µA  
TL  
(2.5V for Port 4[pin 2])  
SRAM (PSD) Standby Current  
I
V
CC  
= 0V  
0.5  
STBY  
(V  
input)  
STBY  
SRAM (PSD) Idle Current  
(V input)  
I
V
> V  
–0.1  
–10  
–20  
0.1  
–55  
–50  
IDLE  
CC STBY  
STBY  
Reset Pin Pull-up Current  
(RESET)  
I
V
= V  
IN SS  
RST  
XTAL1 = V  
XTAL2 = V  
XTAL Feedback Resistor  
Current (XTAL1)  
CC  
I
FR  
SS  
I
V
< V < V  
SS IN CC  
Input Leakage Current  
Output Leakage Current  
–1  
1
µA  
µA  
LI  
I
LO  
0.45 < V  
< V  
OUT CC  
–10  
10  
V
= 3.6V  
CC  
110  
µA  
LVD logic disabled  
(1)  
Power-down Mode  
I
PD  
LVD logic enabled  
180  
10  
5
µA  
mA  
mA  
mA  
mA  
Active (12MHz)  
Idle (12MHz)  
Active (24MHz)  
Idle (24MHz)  
8
4
V
V
= 3.6V  
= 3.6V  
CC  
CC  
(2,3,5)  
I
CC_CPU  
15  
8
20  
10  
www.BDTIC.com/ST  
PLD_TURBO = Off,  
(5)  
0
µA/PT  
µA/PT  
mA  
(4)  
f = 0MHz  
PLD Only  
PLD_TURBO = On,  
200  
400  
f = 0MHz  
I
CC_PSD  
Operating  
(5)  
Supply Current  
During Flash memory  
WRITE/Erase Only  
(DC)  
10  
25  
Flash  
memory  
Read only, f = 0MHz  
f = 0MHz  
0
0
0
0
mA  
mA  
SRAM  
PLD AC Base  
Note 4  
I
CC_PSD  
(5)  
Flash memory AC Adder  
SRAM AC Adder  
1.5  
0.8  
2.0  
1.5  
mA/MHz  
mA/MHz  
(AC)  
Note: 1. I (Power-down Mode) is measured with:  
PD  
2. XTAL1=V ; XTAL2=not connected; RESET=V ; Port 0 =V ; all other pins are disconnected. PLD not in Turbo mode.  
SS  
CC  
CC  
3. I  
(active mode) is measured with:  
CC_CPU  
4. XTAL1 driven with t  
, t  
= 5ns, V = V +0.5V, V = V – 0.5V, XTAL2 = not connected; RESET=V ; Port 0=V ; all  
CLCH CHCL IL SS IH CC SS CC  
other pins are disconnected. I would be slightly higher if a crystal oscillator is used (approximately 1mA).  
CC  
5. I  
(Idle Mode) is measured with:  
CC_CPU  
6. XTAL1 driven with t  
, t  
= 5ns, V = V +0.5V, V = V – 0.5V, XTAL2 = not connected; Port 0 = V  
;
CC  
CLCH CHCL  
IL  
SS  
IH  
CC  
7. RESET=V ; all other pins are disconnected.  
CC  
8. See Figure 68., page 128 for the PLD current calculation.  
9. I/O current = 0mA, all I/O pins are disconnected.  
139/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 71. External Program Memory READ Cycle  
t
t
LLPL  
LHLL  
ALE  
t
t
AVLL  
PLPH  
t
LLIV  
t
PLIV  
PSEN  
t
t
PXAV  
LLAX  
t
PXIZ  
t
AZPL  
PORT 0  
INSTR  
IN  
A0-A7  
A0-A7  
t
AVIV  
t
PXIX  
A8-A11  
A8-A11  
PORT 2  
AI06848  
Table 116. External Program Memory AC Characteristics (with the 5V MCU Module)  
Variable Oscillator  
40MHz Oscillator  
1/t  
= 24 to 40MHz  
Max  
CLCL  
(1)  
Symbol  
Unit  
Parameter  
Min  
Max  
Min  
2t – 15  
CLCL  
t
ALE pulse width  
35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
LHLL  
AVLL  
LLAX  
LLIV  
www.BDTIC.com/ST  
t
t
t
t
t
t
t
t
– 15  
Address set up to ALE  
Address hold after ALE  
ALE Low to valid instruction in  
ALE to PSEN  
10  
10  
CLCL  
t
– 15  
CLCL  
4t  
CLCL  
– 45  
55  
t
– 15  
– 15  
10  
60  
LLPL  
PLPH  
PLIV  
PXIX  
CLCL  
3t  
PSEN pulse width  
CLCL  
3t  
– 45  
– 10  
PSEN to valid instruction in  
Input instruction hold after PSEN  
30  
15  
CLCL  
0
0
(2)  
t
Input instruction float after PSEN  
ns  
t
CLCL  
PXIZ  
(2)  
t
– 5  
Address valid after PSEN  
Address to valid instruction in  
Address float to PSEN  
20  
–5  
ns  
ns  
ns  
t
t
t
CLCL  
PXAV  
5t  
CLCL  
– 55  
70  
AVIV  
–5  
AZPL  
Note: 1. Conditions (in addition to those in Table 109., page 133, V = 4.5 to 5.5V): V = 0V; C for Port 0, ALE and PSEN output is 100pF;  
CC  
SS  
L
C
L
for other outputs is 80pF  
2. Interfacing the uPSD321x Devices to devices with float times up to 20ns is permissible. This limited bus contention does not cause  
any damage to Port 0 drivers.  
140/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 117. External Program Memory AC Characteristics (with the 3V MCU Module)  
Variable Oscillator  
24MHz Oscillator  
1/t  
= 8 to 24MHz  
(1)  
CLCL  
Symbol  
Unit  
Parameter  
Min  
43  
Max  
Min  
– 40  
CLCL  
Max  
t
2t  
t
ALE pulse width  
Address set up to ALE  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
LHLL  
AVLL  
LLAX  
LLIV  
t
t
t
t
t
t
t
– 25  
17  
CLCL  
t
– 25  
Address hold after ALE  
ALE Low to valid instruction in  
ALE to PSEN  
17  
CLCL  
4t  
– 87  
80  
CLCL  
t
– 20  
– 30  
22  
95  
LLPL  
PLPH  
PLIV  
PXIX  
CLCL  
3t  
PSEN pulse width  
CLCL  
3t  
t
– 65  
– 10  
PSEN to valid instruction in  
Input instruction hold after PSEN  
Input instruction float after PSEN  
60  
32  
CLCL  
0
0
(2)  
t
CLCL  
PXIZ  
(2)  
t
– 5  
Address valid after PSEN  
Address to valid instruction in  
Address float to PSEN  
37  
ns  
ns  
ns  
t
t
t
CLCL  
PXAV  
5t  
CLCL  
– 60  
148  
AVIV  
–10  
–10  
AZPL  
Note: 1. Conditions (in addition to those in Table 110., page 133, V = 3.0 to 3.6V): V = 0V; C for Port 0, ALE and PSEN output is 100pF,  
CC  
SS  
L
for 5V devices, and 50pF for 3V devices; C for other outputs is 80pF, for 5V devices, and 50pF for 3V devices)  
L
2. Interfacing the uPSD321x Devices to devices with float times up to 35ns is permissible. This limited bus contention does not cause  
any damage to Port 0 drivers.  
www.BDTIC.com/ST  
141/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 72. External Data Memory READ Cycle  
ALE  
tLHLL  
tWHLH  
PSEN  
tLLDV  
tLLWL  
tRLRH  
RD  
tRHDZ  
tRLDV  
tRLAZ  
tAVLL  
tLLAX2  
tRHDX  
A0-A7 from PCL  
A0-A7 from  
RI or DPL  
DATA IN  
INSTR IN  
PORT 0  
PORT 2  
tAVWL  
tAVDV  
P2.0 to P2.3 or A8-A11 from DPH  
A8-A11 from PCH  
AI07088  
Table 118. External Clock Drive (with the 5V MCU Module)  
Variable Oscillator  
40MHz Oscillator  
1/t  
= 24 to 40MHz  
(1)  
CLCL  
Symbol  
Unit  
Parameter  
Min Max  
Min  
Max  
t
Oscillator period  
25  
41.7  
ns  
ns  
ns  
ns  
ns  
RLRH  
WLWH  
LLAX2  
RHDX  
RHDX  
www.BDTIC.com/ST  
t
t
t
t
t
– t  
– t  
10  
10  
High time  
Low time  
Rise time  
Fall time  
10  
10  
CLCL  
CLCL  
CLCX  
t
CLCX  
Note: 1. Conditions (in addition to those in Table 109., page 133, V = 4.5 to 5.5V): V = 0V; C for Port 0, ALE and PSEN output is 100pF;  
CC  
SS  
L
C
L
for other outputs is 80pF  
Table 119. External Clock Drive (with the 3V MCU Module)  
Variable Oscillator  
24MHz Oscillator  
Min Max  
1/t  
= 8 to 24MHz  
(1)  
CLCL  
Symbol  
Unit  
Parameter  
Min  
Max  
t
Oscillator period  
41.7  
12  
125  
ns  
ns  
ns  
ns  
ns  
RLRH  
WLWH  
LLAX2  
RHDX  
RHDX  
t
t
t
t
t
t
– t  
– t  
12  
12  
High time  
Low time  
Rise time  
Fall time  
CLCL  
CLCX  
12  
CLCL  
CLCX  
Note: 1. Conditions (in addition to those in Table 110., page 133, V = 3.0 to 3.6V): V = 0V; C for Port 0, ALE and PSEN output is 100pF,  
CC  
SS  
L
for 5V devices, and 50pF for 3V devices; C for other outputs is 80pF, for 5V devices, and 50pF for 3V devices)  
L
142/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 73. External Data Memory WRITE Cycle  
ALE  
tLHLL  
tWHLH  
PSEN  
tLLWL  
tWLWH  
WR  
tWHQX  
tQVWX  
tQVWH  
DATA OUT  
tAVLL  
tLLAX  
A0-A7 from  
RI or DPL  
A0-A7 from PCL  
INSTR IN  
PORT 0  
PORT 2  
tAVWL  
P2.0 to P2.3 or A8-A11 from DPH  
A8-A11 from PCH  
AI07089  
Table 120. External Data Memory AC Characteristics (with the 5V MCU Module)  
Variable Oscillator  
40MHz Oscillator  
1/t  
= 24 to 40MHz  
CLCL  
(1)  
Symbol  
Unit  
Parameter  
Min  
120  
120  
10  
Max  
Min  
Max  
t
6t  
6t  
t
– 30  
RD pulse width  
WR pulse width  
Address hold after ALE  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RLRH  
WLWH  
LLAX2  
RHDX  
RHDX  
RHDZ  
LLDV  
CLCL  
CLCL  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
– 30  
– 15  
CLCL  
www.BDTIC.com/ST  
5t  
– 50  
RD to valid data in  
75  
CLCL  
Data hold after RD  
0
0
2t  
8t  
9t  
t
– 12  
– 50  
– 75  
+ 15  
Data float after RD  
38  
150  
150  
90  
CLCL  
CLCL  
CLCL  
ALE to valid data in  
Address to valid data in  
ALE to WR or RD  
AVDV  
LLWL  
3t  
4t  
t
– 15  
– 30  
– 15  
– 20  
– 50  
– 20  
60  
70  
10  
5
CLCL  
CLCL  
Address valid to WR or RD  
WR or RD High to ALE High  
Data valid to WR transition  
Data set up before WR  
Data hold after WR  
AVWL  
WHLH  
QVWX  
QVWH  
WHQX  
RLAZ  
CLCL  
t
+ 15  
40  
CLCL  
CLCL  
CLCL  
t
7t  
t
125  
5
CLCL  
CLCL  
Address float after RD  
0
0
Note: 1. Conditions (in addition to those in Table 109., page 133, V = 4.5 to 5.5V): V = 0V; C for Port 0, ALE and PSEN output is 100pF;  
CC  
SS  
L
C
L
for other outputs is 80pF  
143/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 121. External Data Memory AC Characteristics (with the 3V MCU Module)  
Variable Oscillator  
24MHz Oscillator  
1/t  
= 8 to 24MHz  
(1)  
CLCL  
Symbol  
Unit  
Parameter  
Min  
180  
180  
56  
Max  
Min  
Max  
t
6t  
6t  
2t  
– 70  
RD pulse width  
WR pulse width  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RLRH  
WLWH  
LLAX2  
RHDX  
RHDX  
RHDZ  
LLDV  
CLCL  
CLCL  
CLCL  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
– 70  
– 27  
Address hold after ALE  
RD to valid data in  
5t  
2t  
– 90  
118  
CLCL  
Data hold after RD  
0
0
– 20  
– 133  
– 155  
+ 50  
Data float after RD  
63  
CLCL  
8t  
9t  
t
ALE to valid data in  
200  
220  
175  
CLCL  
CLCL  
CLCL  
Address to valid data in  
ALE to WR or RD  
AVDV  
LLWL  
3t  
4t  
t
– 50  
– 97  
– 25  
– 37  
– 122  
– 27  
75  
67  
17  
5
CLCL  
Address valid to WR or RD  
WR or RD High to ALE High  
Data valid to WR transition  
Data set up before WR  
Data hold after WR  
AVWL  
WHLH  
QVWX  
QVWH  
WHQX  
RLAZ  
CLCL  
t
+ 25  
67  
CLCL  
CLCL  
CLCL  
CLCL  
CLCL  
t
7t  
t
170  
15  
Address float after RD  
0
0
Note: 1. Conditions (in addition to those in Table 110., page 133, V = 3.0 to 3.6V): V = 0V; C for Port 0, ALE and PSEN output is 100pF,  
CC  
SS  
L
Parameter  
for 5V devices, and 50pF for 3V devices; C for other outputs is 80pF, for 5V devices, and 50pF for 3V devices)  
L
Table 122. A/D Analog Specification  
Symbol  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
V
Analog Power Supply Input  
Voltage Range  
AV  
V
V
REF  
SS  
CC  
V
AN  
V
SS  
– 0.3  
AV  
+ 0.3  
REF  
Analog Input Voltage Range  
V
Current Following between V  
CC  
I
200  
µA  
AVDD  
and V  
SS  
CA  
Overall Accuracy  
±2  
±2  
±2  
±2  
±2  
±2  
20  
l.s.b.  
l.s.b.  
l.s.b.  
l.s.b.  
l.s.b.  
l.s.b.  
µs  
IN  
N
NLE  
Non-Linearity Error  
N
Differential Non-Linearity Error  
Zero-Offset Error  
Full Scale Error  
DNLE  
N
ZOE  
N
FSE  
N
GE  
Gain Error  
T
Conversion Time  
at 8MHz clock  
CONV  
144/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 74. Input to Output Disable / Enable  
INPUT  
tER  
tEA  
INPUT TO  
OUTPUT  
ENABLE/DISABLE  
AI02863  
Table 123. CPLD Combinatorial Timing (5V Devices)  
Slew  
PT  
Aloc  
Turbo  
Off  
Symbol  
Parameter  
Conditions  
Min  
Max  
20  
Unit  
ns  
(1)  
rate  
CPLD Input Pin/Feedback to  
CPLD Combinatorial Output  
(2)  
+ 2  
+ 10  
+ 10  
+ 10  
+ 10  
+ 10  
– 2  
t
PD  
CPLD Input to CPLD Output  
Enable  
t
t
t
t
t
21  
– 2  
– 2  
– 2  
ns  
EA  
CPLD Input to CPLD Output  
Disable  
21  
ns  
ER  
CPLD Register Clear or Preset  
Delay  
21  
ns  
ARP  
ARPW  
ARD  
CPLD Register Clear or Preset  
Pulse Width  
10  
ns  
Any  
macrocell  
CPLD Array Delay  
11  
www.BDTIC.com/ST  
+ 2  
ns  
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount  
2. t for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial  
PD  
output (80-pin package only)  
Table 124. CPLD Combinatorial Timing (3V Devices)  
Slew  
PT  
Aloc  
Turbo  
Off  
Symbol  
Parameter  
Conditions  
Min  
Max  
40  
Unit  
ns  
(1)  
rate  
CPLD Input Pin/Feedback to  
CPLD Combinatorial Output  
(2)  
+ 4  
+ 20  
+ 20  
+ 20  
+ 20  
+ 20  
– 6  
t
PD  
CPLD Input to CPLD Output  
Enable  
t
t
t
t
t
43  
– 6  
– 6  
– 6  
ns  
EA  
CPLD Input to CPLD Output  
Disable  
43  
ns  
ER  
CPLD Register Clear or  
Preset Delay  
40  
ns  
ARP  
ARPW  
ARD  
CPLD Register Clear or  
Preset Pulse Width  
25  
ns  
Any  
macrocell  
CPLD Array Delay  
25  
+ 4  
ns  
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount  
2. t for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial  
PD  
output (80-pin package only)  
145/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 75. Synchronous Clock Mode Timing – PLD  
t
t
CL  
CH  
CLKIN  
INPUT  
t
S
t
H
t
CO  
REGISTERED  
OUTPUT  
AI02860  
Table 125. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)  
Slew  
PT  
Aloc  
Turbo  
Off  
Symbol  
Parameter  
Conditions  
Min  
Max  
40.0  
66.6  
83.3  
Unit  
MHz  
MHz  
MHz  
(1)  
rate  
Maximum Frequency  
External Feedback  
1/(t +t  
)
CO  
S
Maximum Frequency  
f
1/(t +t –10)  
CO  
MAX  
S
Internal Feedback (f  
)
CNT  
Maximum Frequency  
Pipelined Data  
1/(t +t  
)
CH CL  
t
t
t
t
t
Input Setup Time  
12  
0
+ 2  
+ 10  
ns  
ns  
ns  
ns  
ns  
S
Input Hold Time  
H
www.BDTIC.com/ST  
Clock High Time  
Clock Input  
Clock Input  
Clock Input  
6
CH  
CL  
CO  
Clock Low Time  
6
Clock to Output Delay  
13  
– 2  
Any  
macrocell  
t
t
CPLD Array Delay  
11  
+ 2  
ns  
ns  
ARD  
(2)  
t
+t  
CH CL  
12  
MIN  
Minimum Clock Period  
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.  
2. CLKIN (PD1) t = t + t  
.
CL  
CLCL  
CH  
146/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 126. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)  
Slew  
PT  
Aloc  
Turbo  
Off  
Symbol  
Parameter  
Conditions  
Min  
Max  
22.2  
28.5  
40.0  
Unit  
MHz  
MHz  
MHz  
(1)  
rate  
Maximum Frequency  
External Feedback  
1/(t +t  
)
CO  
S
Maximum Frequency  
f
1/(t +t –10)  
CO  
MAX  
S
Internal Feedback (f  
)
CNT  
Maximum Frequency  
Pipelined Data  
1/(t +t  
)
CH CL  
t
t
t
t
t
Input Setup Time  
Input Hold Time  
Clock High Time  
Clock Low Time  
Clock to Output Delay  
20  
0
+ 4  
+ 20  
ns  
ns  
ns  
ns  
ns  
S
H
Clock Input  
Clock Input  
Clock Input  
15  
10  
CH  
CL  
CO  
25  
25  
– 6  
Any  
macrocell  
t
t
CPLD Array Delay  
+ 4  
ns  
ns  
ARD  
(2)  
t +t  
CH CL  
25  
MIN  
Minimum Clock Period  
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.  
2. CLKIN (PD1) t = t + t  
.
CL  
CLCL  
CH  
Figure 76. Asynchronous RESET / Preset  
tARPW  
RESET/PRESET  
www.BDTIC.com/ST  
REGISTER  
OUTPUT  
INPUT  
tARP  
AI02864  
Figure 77. Asynchronous Clock Mode Timing (Product Term Clock)  
tCHA  
tCLA  
CLOCK  
INPUT  
tSA  
tHA  
tCOA  
REGISTERED  
OUTPUT  
AI02859  
147/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 127. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)  
PT  
Turbo Slew  
Symbol  
Parameter  
Conditions  
Min  
Max  
38.4  
62.5  
71.4  
Unit  
MHz  
MHz  
MHz  
Aloc  
Off  
Rate  
Maximum Frequency  
External Feedback  
1/(t +t  
)
SA COA  
Maximum Frequency  
f
1/(t +t  
–10)  
)
MAXA  
SA COA  
Internal Feedback (f  
)
CNTA  
Maximum Frequency  
Pipelined Data  
1/(t  
+t  
CHA CLA  
t
t
t
t
t
t
t
Input Setup Time  
7
8
9
9
+ 2  
+ 10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SA  
Input Hold Time  
HA  
Clock Input High Time  
Clock Input Low Time  
Clock to Output Delay  
CPLD Array Delay  
Minimum Clock Period  
+ 10  
+ 10  
+ 10  
CHA  
CLA  
COA  
ARDA  
MINA  
21  
11  
– 2  
Any macrocell  
+ 2  
1/f  
CNTA  
16  
Table 128. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)  
PT  
Turbo Slew  
Symbol  
Parameter  
Conditions  
Min  
Max  
21.7  
27.8  
Unit  
MHz  
MHz  
MHz  
Aloc  
Off  
Rate  
Maximum Frequency  
External Feedback  
1/(t +t  
)
SA COA  
Maximum Frequency  
f
1/(t +t  
–10)  
MAXA  
SA COA  
Internal Feedback (f  
)
CNTA  
www.BDTIC.com/ST  
Maximum Frequency  
Pipelined Data  
1/(t  
+t  
)
33.3  
CHA CLA  
t
t
t
t
t
t
t
Input Setup Time  
Input Hold Time  
10  
12  
17  
13  
+ 4  
+ 20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SA  
HA  
Clock High Time  
+ 20  
+ 20  
+ 20  
CHA  
CLA  
COA  
ARD  
MINA  
Clock Low Time  
Clock to Output Delay  
CPLD Array Delay  
Minimum Clock Period  
36  
25  
– 6  
Any macrocell  
+ 4  
1/f  
CNTA  
36  
148/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 78. Input Macrocell Timing (Product Term Clock)  
t
t
INL  
INH  
PT CLOCK  
INPUT  
t
t
IH  
IS  
OUTPUT  
t
INO  
AI03101  
Table 129. Input Macrocell Timing (5V Devices)  
PT  
Aloc  
Turbo  
Off  
Symbol  
Parameter  
Input Setup Time  
Conditions  
Min  
Max  
Unit  
t
0
15  
9
ns  
ns  
ns  
ns  
ns  
IS  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
t
t
t
t
Input Hold Time  
+ 10  
IH  
NIB Input High Time  
NIB Input Low Time  
INH  
INL  
INO  
9
NIB Input to Combinatorial Delay  
34  
+ 2  
+ 10  
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t  
and t  
.
LXAX  
AVLX  
www.BDTIC.com/ST  
Table 130. Input Macrocell Timing (3V Devices)  
PT  
Aloc  
Turbo  
Off  
Symbol  
Parameter  
Input Setup Time  
Conditions  
Min  
Max  
Unit  
t
0
ns  
ns  
ns  
ns  
ns  
IS  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
t
t
t
t
Input Hold Time  
25  
12  
12  
+ 20  
IH  
NIB Input High Time  
NIB Input Low Time  
INH  
INL  
INO  
NIB Input to Combinatorial Delay  
46  
+ 4  
+ 20  
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t  
and t  
.
LXAX  
AVLX  
149/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 131. Program, WRITE and Erase Times (5V Devices)  
Symbol  
Parameter  
Min.  
Typ.  
8.5  
3
Max.  
30  
Unit  
Flash Program  
s
(1)  
s
Flash Bulk Erase (pre-programmed)  
Flash Bulk Erase (not pre-programmed)  
Sector Erase (pre-programmed)  
Sector Erase (not pre-programmed)  
Byte Program  
5
s
s
t
t
t
1
30  
WHQV3  
WHQV2  
WHQV1  
2.2  
14  
s
150  
µs  
Program / Erase Cycles (per Sector)  
Sector Erase Time-out  
100,000  
cycles  
µs  
t
t
100  
WHWLO  
Q7VQV  
(2)  
30  
ns  
DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)  
Note: 1. Programmed to all zero before erase.  
2. The polling status, DQ7, is valid t  
time units before the data byte, DQ0-DQ7, is valid for reading.  
Q7VQV  
Table 132. Program, WRITE and Erase Times (3V Devices)  
Symbol  
Parameter  
Min.  
Typ.  
8.5  
3
Max.  
30  
Unit  
Flash Program  
s
(1)  
s
s
Flash Bulk Erase (pre-programmed)  
Flash Bulk Erase (not pre-programmed)  
Sector Erase (pre-programmed)  
Sector Erase (not pre-programmed)  
Byte Program  
5
t
t
t
1
30  
s
WHQV3  
WHQV2  
WHQV1  
2.2  
s
14  
150  
µs  
cycles  
µs  
ns  
www.BDTIC.com/ST  
Program / Erase Cycles (per Sector)  
Sector Erase Time-out  
100,000  
t
t
100  
WHWLO  
Q7VQV  
(2)  
30  
DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)  
Note: 1. Programmed to all zero before erase.  
2. The polling status, DQ7, is valid t  
time units before the data byte, DQ0-DQ7, is valid for reading.  
Q7VQV  
150/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 79. Peripheral I/O READ Timing  
ALE  
ADDRESS  
DATA VALID  
A/D BUS  
t
(PA)  
(PA)  
AVQV  
t
SLQV  
CSI  
RD  
t
(PA)  
RLQV  
t
(PA)  
RHQZ  
t
(PA)  
DVQV  
DATA ON PORT A  
AI06610  
Table 133. Port A Peripheral Data Mode READ Timing (5V Devices)  
Turbo  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
Off  
+ 10  
+ 10  
Address Valid to Data  
t
37  
ns  
AVQV–PA  
(Note 1)  
Vawlid ww.BDTIC.com/ST  
t
t
t
t
CSI Valid to Data Valid  
RD to Data Valid  
27  
32  
22  
23  
ns  
ns  
ns  
ns  
SLQV–PA  
RLQV–PA  
DVQV–PA  
RHQZ–PA  
(Note 2)  
Data In to Data Out Valid  
RD to Data High-Z  
Note: 1. Any input used to select Port A Data Peripheral Mode.  
2. Data is already stable on Port A.  
Table 134. Port A Peripheral Data Mode READ Timing (3V Devices)  
Turbo  
Off  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
t
t
t
t
t
Address Valid to Data Valid  
CSI Valid to Data Valid  
RD to Data Valid  
50  
37  
45  
38  
36  
+ 20  
+ 20  
ns  
ns  
ns  
ns  
ns  
AVQV–PA  
SLQV–PA  
RLQV–PA  
DVQV–PA  
RHQZ–PA  
(Note 1)  
(Note 2)  
Data In to Data Out Valid  
RD to Data High-Z  
Note: 1. Any input used to select Port A Data Peripheral Mode.  
2. Data is already stable on Port A.  
151/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 80. Peripheral I/O WRITE Timing  
ALE  
ADDRESS  
DATA OUT  
A/D BUS  
tWHQZ (PA)  
tWLQV (PA)  
WR  
tDVQV (PA)  
PORT A  
DATA OUT  
AI06611  
Table 135. Port A Peripheral Data Mode WRITE Timing (5V Devices)  
Symbol  
WLQV–PA  
DVQV–PA  
WHQZ–PA  
Parameter  
WR to Data Propagation Delay  
Data to Port A Data Propagation Delay  
WR Invalid to Port A Tri-state  
Conditions  
Min  
Max  
25  
Unit  
ns  
t
t
t
22  
ns  
(Note 1)  
20  
ns  
Note: 1. Data stable on Port 0 pins to data on Port A.  
Table 136. Port A Peripheral Data Mode WRITE Timing (3V Devices)  
www.BDTIC.com/ST  
Symbol  
WLQV–PA  
DVQV–PA  
WHQZ–PA  
Parameter  
WR to Data Propagation Delay  
Data to Port A Data Propagation Delay  
WR Invalid to Port A Tri-state  
Conditions  
Min  
Max  
42  
Unit  
ns  
t
t
t
38  
ns  
(Note 1)  
33  
ns  
Note: 1. Data stable on Port 0 pins to data on Port A.  
152/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 81. Reset (RESET) Timing  
VCC(min)  
VCC  
t
t
OPR  
t
t
NLNH-PO  
NLNH  
OPR  
Power-On Reset  
Warm Reset  
RESET  
AI07437  
Table 137. Reset (RESET) Timing (5V Devices)  
Symbol  
Parameter  
Conditions  
Min  
150  
1
Max  
Unit  
(1)  
t
t
t
ns  
ms  
ns  
NLNH  
RESET Active Low Time  
Power-on Reset Active Low Time  
RESET High to Operational Device  
NLNH–PO  
OPR  
120  
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.  
Table 138. Reset (RESET) Timing (3V Devices)  
Symbol  
Parameter  
Conditions  
Min  
300  
1
Max  
Unit  
ns  
(1)  
t
t
t
NLNH  
RESET Active Low Time  
Power-on Reset Active Low Time  
ms  
ns  
NLNH–PO  
OPR  
www.BDTIC.com/ST  
RESET High to Operational Device  
300  
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.  
Table 139. V  
Symbol  
Definitions Timing (5V Devices)  
Parameter  
STBYON  
Conditions  
Min  
Typ  
Max  
Unit  
t
V
V
Detection to V  
Output High  
STBYON  
20  
µs  
BVBH  
STBY  
(Note 1)  
Off Detection to V  
Output  
STBY  
STBYON  
t
20  
µs  
BXBL  
(Note 1)  
Low  
Note: 1. V  
timing is measured at V ramp rate of 2ms.  
CC  
STBYON  
Table 140. V  
Symbol  
Timing (3V Devices)  
Parameter  
STBYON  
Conditions  
Min  
Typ  
Max  
Unit  
t
V
V
Detection to V  
Output High  
STBYON  
20  
µs  
BVBH  
STBY  
(Note 1)  
Off Detection to V  
Output  
STBY  
STBYON  
t
20  
µs  
BXBL  
(Note 1)  
Low  
Note: 1. V  
timing is measured at V ramp rate of 2ms.  
CC  
STBYON  
153/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 82. ISC Timing  
tISCCH  
TCK  
tISCCL  
tISCPSU  
tISCPH  
TDI/TMS  
t ISCPZV  
tISCPCO  
ISC OUTPUTS/TDO  
tISCPVZ  
ISC OUTPUTS/TDO  
AI02865  
Table 141. ISC Timing (5V Devices)  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
MHz  
ns  
t
Clock (TCK, PC1) Frequency (except for PLD)  
Clock (TCK, PC1) High Time (except for PLD)  
20  
ISCCF  
(Note 1)  
(Note 1)  
t
t
t
t
23  
ISCCH  
ISCCL  
www.BDTIC.com/ST  
Clock (TCK, PC1) Low Time (except for PLD)  
Clock (TCK, PC1) Frequency (PLD only)  
Clock (TCK, PC1) High Time (PLD only)  
23  
ns  
(Note 1)  
(Note 2)  
(Note 2)  
(Note 2)  
2
MHz  
ns  
ISCCFP  
ISCCHP  
240  
t
t
t
t
t
t
Clock (TCK, PC1) Low Time (PLD only)  
ISC Port Set Up Time  
240  
7
ns  
ns  
ns  
ns  
ns  
ns  
ISCCLP  
ISCPSU  
ISCPH  
ISC Port Hold Up Time  
5
ISC Port Clock to Output  
21  
21  
21  
ISCPCO  
ISCPZV  
ISCPVZ  
ISC Port High-Impedance to Valid Output  
ISC Port Valid Output to High-Impedance  
Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.  
2. For Program or Erase PLD only.  
154/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 142. ISC Timing (3V Devices)  
Symbol  
Parameter  
Conditions  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 2)  
(Note 2)  
(Note 2)  
Min  
Max  
Unit  
MHz  
ns  
t
Clock (TCK, PC1) Frequency (except for PLD)  
Clock (TCK, PC1) High Time (except for PLD)  
Clock (TCK, PC1) Low Time (except for PLD)  
Clock (TCK, PC1) Frequency (PLD only)  
Clock (TCK, PC1) High Time (PLD only)  
12  
ISCCF  
t
t
t
t
40  
40  
ISCCH  
ISCCL  
ns  
2
MHz  
ns  
ISCCFP  
ISCCHP  
240  
t
t
t
t
t
t
Clock (TCK, PC1) Low Time (PLD only)  
ISC Port Set Up Time  
240  
12  
5
ns  
ns  
ns  
ns  
ns  
ns  
ISCCLP  
ISCPSU  
ISCPH  
ISC Port Hold Up Time  
ISC Port Clock to Output  
30  
30  
30  
ISCPCO  
ISCPZV  
ISCPVZ  
ISC Port High-Impedance to Valid Output  
ISC Port Valid Output to High-Impedance  
Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.  
2. For Program or Erase PLD only.  
Figure 83. MCU Module AC Measurement I/O Waveform  
V
– 0.5V  
CC  
0.2 V  
0.2 V  
+ 0.9V  
CC  
Test Points  
– 0.1V  
CC  
www.BDTIC.com/ST  
0.45V  
AI06650  
Note: AC inputs during testing are driven at V –0.5V for a logic '1,' and 0.45V for a logic '0.'  
CC  
Timing measurements are made at V (min) for a logic '1,' and V (max) for a logic '0'  
IH  
IL  
Figure 84. PSD MODULE AC Float I/O Waveform  
V
V
– 0.1V  
OH  
OL  
V
V
+ 0.1V  
LOAD  
Test Reference Points  
– 0.1V  
– 0.1V  
+ 0.1V  
LOAD  
CC  
0.2 V  
AI06651  
Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to  
float when a 100mV change from the loaded V or V level occurs  
OH  
OL  
I
and I 20mA  
OH  
OL  
155/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 85. External Clock Cycle  
Figure 86. Recommended Oscillator Circuits  
Note: C1, C2 = 30pF ± 10pF for crystals  
For ceramic resonators, contact resonator manufacturer  
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator  
have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.  
www.BDTIC.com/ST  
Figure 87. PSD MODULE AC Measurement I/O  
Waveform  
Figure 88. PSD MODULEAC Measurement  
Load Circuit  
2.01 V  
3.0V  
195  
Test Point  
1.5V  
Device  
Under Test  
0V  
CL = 30 pF  
(Including Scope and  
AI03103b  
Jig Capacitance)  
AI03104b  
Table 143. Capacitance  
(1)  
Symbol  
Parameter  
Test Condition  
Max.  
Unit  
pF  
Typ.  
C
V
= 0V  
= 0V  
Input Capacitance (for input pins)  
4
6
IN  
IN  
Output Capacitance (for input/  
output pins)  
pF  
C
V
OUT  
8
12  
OUT  
Note: Sampled only, not 100% tested.  
1. Typical values are for T = 25°C and nominal supply voltages.  
A
156/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
PACKAGE MECHANICAL INFORMATION  
Figure 89. TQFP52 – 52-lead Plastic Thin, Quad, Flat Package Outline  
D
D1  
D2  
A2  
e
b
Ne  
E2 E1 E  
N
1
Nd  
A
CP  
L1  
www.BDTIC.com/ST  
A1  
c
α
L
QFP-A  
Note: Drawing is not to scale.  
157/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 144. TQFP52 – 52-lead Plastic Thin, Quad, Flat Package Mechanical Data  
mm  
Min  
inches  
Min  
Symb  
Typ  
Max  
1.75  
0.020  
1.55  
0.04  
0.23  
Typ  
Max  
0.069  
0.008  
0.061  
0.016  
0.009  
A
A1  
A2  
b
0.05  
1.25  
0.02  
0.07  
0.002  
0.049  
0.007  
0.002  
c
D
12.00  
10.00  
0.473  
0.394  
D1  
D2  
E
12.00  
10.00  
0.473  
0.394  
E1  
E2  
e
0.65  
0.45  
0.75  
0.026  
0.018  
0.030  
L
L1  
α
1.00  
0.039  
0°  
7°  
0°  
7°  
n
52  
13  
52  
Nd  
Ne  
CP  
13  
www.BDTIC.com/ST  
13  
13  
0.10  
0.004  
158/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Figure 90. TQFP80 – 80-lead Plastic Thin, Quad, Flat Package Outline  
D
D1  
D2  
A2  
e
b
Ne  
E2 E1 E  
N
1
Nd  
A
CP  
L1  
www.BDTIC.com/ST  
c
A1  
α
L
QFP-A  
Note: Drawing is not to scale.  
159/163  
 
uPSD3212A, uPSD3212C, uPSD3212CV  
Table 145. TQFP80 – 80-lead Plastic Thin, Quad, Flat Package Mechanical Data  
mm  
Min  
inches  
Symb  
Typ  
Max  
1.60  
0.15  
1.45  
0.27  
0.20  
Typ  
Min  
Max  
A
A1  
A2  
b
0.063  
0.05  
1.35  
0.17  
0.09  
0.002  
0.006  
1.40  
0.22  
0.055  
0.009  
0.053  
0.057  
0.007  
0.011  
c
0.004  
0.008  
D
14.00  
12.00  
9.50  
14.00  
12.00  
9.50  
0.50  
0.60  
1.00  
3.5  
0.551  
0.472  
0.374  
0.551  
0.472  
0.374  
0.020  
0.024  
0.039  
3.5  
D1  
D2  
E
E1  
E2  
e
L
0.45  
0.75  
0.018  
0.030  
L1  
α
0°  
7°  
0°  
80  
20  
7°  
n
80  
20  
Nd  
Ne  
CP  
www.BDTIC.com/ST  
20  
20  
0.08  
0.003  
160/163  
 
 
uPSD3212A, uPSD3212C, uPSD3212CV  
PART NUMBERING  
Table 146. Ordering Information Scheme  
Example:  
uPSD  
3
2
1
2
C
V
24  
U
6
T
Device Type  
uPSD = Microcontroller PSD  
Family  
3 = 8032 core  
PLD Size  
2 = 16 Macrocells  
SRAM Size  
1 = 2K bytes  
Main Flash Memory Size  
2 = 64K bytes  
IP Mix  
2
A = USB, I C, PWM, ADC, (2) UARTs  
Supervisor (Reset Out, Reset In, LVD, WD)  
2
C = I C, PWM, ADC, (2) UARTs  
Supervisor (Reset Out, Reset In, LVD, WD)  
www.BDTIC.com/ST  
Operating Voltage  
blank = V = 4.5 to 5.5V  
CC  
V = V = 3.0 to 3.6V  
CC  
Speed  
–24 = 24MHz  
–40 = 40MHz  
Package  
T = 52-pin TQFP  
U = 80-pin TQFP  
Temperature Range  
6 = –40 to 85°C  
Shipping Option  
T = Tape and Reel Packing  
For other options, or for more information on any aspect of this device, please contact the ST Sales Office  
nearest you.  
161/163  
 
   
uPSD3212A, uPSD3212C, uPSD3212CV  
REVISION HISTORY  
Table 147. Document Revision History  
Date  
Version  
Revision Details  
18-Dec-2002  
1.0  
First Issue  
Updates: port information (Table 30); interface information (Figure 30, Table 44); remove  
programming guide; PSD Module information (Table 82); PLD information (Figure 55);  
electrical characteristics (Table 114, 115, 131, 132)  
04-Mar-03  
1.1  
02-Sep-03  
03-Feb-04  
02-July-04  
04-Nov-04  
1.2  
2.0  
3.0  
4.0  
Update references for Product Catalog  
Reformatted; correct package dimensions (Table 145)  
Reformatted; add EMC characteristics information (Table 106, 107, 108)  
Updates per requested data brief changes (Figure 3, 4; Table 1, 2, 113)  
Add USB feature to document (Figure 2, 3, 4, 15, 16, 18, 20, 40, 41, 42, 43, 44, 45; Table  
1, 2, 15, 16, 18, 19, 21, 23, 24, 25, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,  
74, 75, 76, 77, 78, 79, 146)  
03-Dec-04  
5.0  
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uPSD3212A, uPSD3212C, uPSD3212CV  
www.BDTIC.com/ST  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics.  
All other names are the property of their respective owners  
© 2004 STMicroelectronics - All rights reserved  
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